Editing VMEbus (section)

== Description ==
In many ways the VMEbus is equivalent or analogous to the pins of the [[Motorola 68000|68000]] run out onto a [[backplane]].

However, one of the key features of the 68000 is a flat [[32-bit]] memory model, free of [[memory segment]]ation and other "anti-features". The result is that, while VME is very 68000-like, the 68000 is generic enough to make this not an issue in most cases.

Like the 68000, VME uses separate 32-bit data and address buses. The 68000 address bus is actually 24-bit and the data bus 16-bit (although it is 32/32 internally) but the designers were already looking towards a full 32-bit implementation.

In order to allow both bus widths, VME uses two different Eurocard connectors, P1 and P2. P1 contains three rows of 32 pins each, implementing the first 24 address bits, 16 data bits and all of the control signals. P2 contains one more row, which includes the remaining 8 address bits and 16 data bits.

A block transfer protocol allows several bus transfers to occur with a single address cycle.  In block transfer mode, the first transfer includes an address cycle and subsequent transfers require only data cycles. The slave is responsible for ensuring that these transfers use successive addresses.

Bus masters can release the bus in two ways. With Release When Done (RWD), the master releases the bus when it completes a transfer and must re-arbitrate for the bus before every subsequent transfer. With Release On Request (ROR), the master retains the bus by continuing to assert BBSY* between transfers.  ROR allows the master to retain control over the bus until a Bus Clear (BCLR*) is asserted by another master that wishes to arbitrate for the bus.  Thus a master that generates bursts of traffic can optimize ''its'' performance by arbitrating for the bus on only the first transfer of each burst.  This decrease in transfer latency comes at the cost of somewhat higher transfer latency for other masters.

Address modifiers are used to divide the VME bus address space into several distinct sub-spaces. The address modifier is a 6 bit wide set of signals on the backplane.  Address modifiers specify the number of significant address bits, the privilege mode (to allow processors to distinguish between bus accesses by user-level or system-level software), and whether or not the transfer is a block transfer.
Below is an incomplete table of address modifiers:

{| class="wikitable"
|-
! Hex Code
! Function
! Explanation
|-
| 3f
| Standard Supervisory block transfer
| Block transfer A24, privileged
|-
| 3e
| Standard Supervisory Program access
| A24 instruction access, privileged
|-
| 3d 
| Standard Supervisor Data Access
| A24 data access, privileged
|-
| 3b
| Standard Non-privileged block transfer
| A24 block transfer for normal programs
|-
| 3a
| Standard Non-privileged Program access
| A24 instruction access, non-privileged
|-
| 39
| Standard non-privileged Data Access
| A24 data access, non-privileged
|-
| 2d 
| Short supervisory Access
| A16 privileged access.
|-
| 29
| Short non-privileged Access
| A16 non-privileged access.
|-
| 0f
| Extended supervisory Block transfer
| A32 privileged block transfer.
|-
| 0e
| Extended supervisory Program access
| A32 privileged instruction access.
|-
| 0d
| Extended supervisory Data Access.
| A32 privileged data access.
|-
| 0b
| Extended Non-privileged Block transfer
| A32 non-privileged block transfer.
|-
| 0a
| Extended Non-privileged Program access
| A32 non-privileged instruction access.
|-
| 09
| Extended non-privileged data access.
| A32 non-privileged data access.
|-
|'''Note'''
|
|''A<sub>n</sub> as in A16, A24, A32 refers to the width of the address''
|}

On the VME bus, all transfers are [[Direct Memory Access|DMA]] and every card is a master or slave. In most bus standards, there is a considerable amount of complexity added in order to support various transfer types and master/slave selection. For instance, with the [[ISA bus]], both of these features had to be added alongside the existing "channels" model, whereby all communications was handled by the host [[Central processing unit|CPU]]. This makes VME considerably simpler at a conceptual level while being more powerful, though it requires more complex controllers on each card.