Editing SuperH (section)

===SH-3===
A few years later, the SH-3 core was added to the family; new features included another [[interrupt]] concept, a [[memory management unit]] (MMU), and a modified cache concept. These features required an extended instruction set, adding six new instructions for a total of 68.{{sfn|Program|1996|p=1}} The SH-3 was [[Endianness#Bi-endian hardware|bi-endian]], running in either big-endian or little-endian byte ordering.

The SH-3 core also added a [[digital signal processing|DSP]] extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated [[Multiply–accumulate|MAC]]-type DSP engine, this core unified the DSP and the RISC processor world. A derivative of the DSP was also used with the original SH-2 core.

Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide.<ref>{{cite web |url=http://segatech.com/technical/cpu/tech_sh4.html |archive-url=https://web.archive.org/web/20160305103423/http://segatech.com/technical/cpu/tech_sh4.html |archive-date=5 March 2016 |title=360-MIPS SuperH RISC Processor Enables Personal Access Systems SH7750 Launches the SH-4 Series |date = November 1997 }}</ref>