Editing StrongARM (section)

===Description===
{{Unreferenced section|date=December 2018}}
The SA-110 had a simple [[microarchitecture]]. It was a [[Scalar processor|scalar]] design that executed instructions [[Out-of-order execution|in-order]] with a five-stage [[classic RISC pipeline]]. The microprocessor was partitioned into several blocks, the IBOX, EBOX, IMMU, DMMU, BIU, WB and PLL. The IBOX contained hardware that operated in the first two stages of the pipeline such as the [[program counter]]. It fetched, decoded and issued instructions. Instruction fetch occurs during the first stage, decode and issue during the second. The IBOX decodes the more complex instructions in the ARM instruction set by translating them into sequences of simpler instructions. The IBOX also handled branch instructions. The SA-110 did not have [[branch prediction]] hardware, but had mechanisms for their speedy processing.

Execution starts at stage three. The hardware that operates during this stage is contained in the EBOX, which comprises the [[register file]], [[arithmetic logic unit]] (ALU), [[barrel shifter]], [[Binary multiplier|multiplier]] and condition code logic. The register file had three read ports and two write ports. The ALU and barrel shifter executed instructions in a single cycle. The multiplier is not pipelined and has a latency of multiple cycles.

The IMMU and DMMU are [[memory management unit]]s for instructions and data, respectively. Each MMU contained a 32-entry [[CPU cache#Associativity|fully associative]] [[translation lookaside buffer]] (TLB) that can map 4&nbsp;KB, 64&nbsp;KB or 1&nbsp;MB [[Page (computer science)|page]]s. The write buffer (WB) has eight 16-byte entries. It enables the pipelining of stores. The bus interface unit (BIU) provided the SA-110 with an external interface.

The [[Phase-locked loop|PLL]] generates the internal [[clock signal]] from an external 3.68&nbsp;MHz clock signal. It was not designed by DEC, but was contracted to the Centre Suisse d'Electronique et de Microtechnique (CSEM) located in [[Neuchâtel]], [[Switzerland]].

The instruction [[CPU cache|cache]] and data cache each have a capacity of 16&nbsp;KB and are 32-way [[set-associative]] and virtually addressed. The SA-110 was designed to be used with slow (and therefore low-cost) memory and therefore the high set associativity allows a higher hit rate than competing designs, and the use of virtual addresses allows memory to be simultaneously cached and uncached. The caches are responsible for most of the transistor count and they take up half the die area.

The SA-110 contained 2.5 million transistors and is 7.8&nbsp;mm by 6.4&nbsp;mm large (49.92&nbsp;mm<sup>2</sup>). It was fabricated by DEC in its proprietary CMOS-6 process at its Fab 6 [[Semiconductor fabrication plant|fab]] in Hudson, Massachusetts. CMOS-6 was DEC's sixth-generation [[CMOS|complementary metal&ndash;oxide&ndash;semiconductor (CMOS)]] process. CMOS-6 has a 0.35&nbsp;μm feature size, a 0.25&nbsp;μm effective channel length but for use with the SA-110, only three levels of [[aluminium interconnect]]. It used a power supply with a variable voltage of 1.2 to 2.2 [[volt]]s (V) to enable designs to find a balance between power consumption and performance (higher voltages enable higher clock rates). The SA-110 was packaged in a 144-pin [[Thin Quad Flat Pack|thin quad flat pack]] (TQFP).