Editing Semiconductor device fabrication (section)

===20th century===
[[File:1957(Figure 9)-Gate oxide transistor by Frosch and Derrick.png|thumb|245x245px|A diagram of the semiconductor oxide transistors made by Frosch and Derick in 1957<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650}}</ref>]]
In 1955, [[Carl Frosch]] and Lincoln Derick, working at [[Bell Telephone Laboratories]], accidentally grew a layer of silicon dioxide over the silicon wafer, for which they observed surface passivation effects.<ref name=":0">{{Cite journal |last1=Huff |first1=Howard |last2=Riordan |first2=Michael |date=2007-09-01 |title=Frosch and Derick: Fifty Years Later (Foreword) |url=https://iopscience.iop.org/article/10.1149/2.F02073IF |journal=The Electrochemical Society Interface |volume=16 |issue=3 |pages=29 |doi=10.1149/2.F02073IF |issn=1064-8208}}</ref><ref>{{Cite patent|number=US2802760A|title=Oxidation of semiconductive surfaces for controlled diffusion|gdate=1957-08-13|invent1=Lincoln|invent2=Frosch|inventor1-first=Derick|inventor2-first=Carl J.|url=https://patents.google.com/patent/US2802760A}}</ref> By 1957 Frosch and Derick, using masking and predeposition, were able to manufacture silicon dioxide transistors; the first planar field effect transistors, in which drain and source were adjacent at the same surface.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650}}</ref> At Bell Labs, the importance of their discoveries was immediately realized. Memos describing the results of their work circulated around Bell Labs before being formally published in 1957. At [[Shockley Semiconductor Laboratory|Shockley Semiconductor]], Shockley had circulated the preprint of their article in December 1956 to all his senior staff, including [[Jean Hoerni]],<ref name="Moskowitz">{{cite book |last1=Moskowitz |first1=Sanford L. |url=https://books.google.com/books?id=2STRDAAAQBAJ&pg=PA168 |title=Advanced Materials Innovation: Managing Global Technology in the 21st century |date=2016 |publisher=[[John Wiley & Sons]] |isbn=978-0-470-50892-3 |page=168}}</ref><ref>{{cite book |author1=Christophe Lécuyer |url=https://books.google.com/books?id=LaZpUpkG70QC&pg=PA62 |title=Makers of the Microchip: A Documentary History of Fairchild Semiconductor |author2=David C. Brook |author3=Jay Last |date=2010 |publisher=MIT Press |isbn=978-0-262-01424-3 |pages=62–63}}</ref><ref>{{cite book |last1=Claeys |first1=Cor L. |url=https://books.google.com/books?id=bu22JNYbE5MC&pg=PA27 |title=ULSI Process Integration III: Proceedings of the International Symposium |date=2003 |publisher=[[The Electrochemical Society]] |isbn=978-1-56677-376-8 |pages=27–30}}</ref><ref name="Lojek120">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |page=120}}</ref> who would later invent the [[planar process]] in 1959 while at [[Fairchild Semiconductor]].<ref>{{patent|US|3025589|Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959}}</ref><ref>{{patent|US|3064167|Hoerni, J. A.: "Semiconductor device" filed May 15, 1960}}</ref>

In 1948, Bardeen patented an insulated-gate transistor (IGFET) with an inversion layer; Bardeen's concept forms the basis of [[MOSFET]] technology today.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> An improved type of MOSFET technology, [[CMOS]], was developed by [[Chih-Tang Sah]] and [[Frank Wanlass]] at [[Fairchild Semiconductor]] in 1963.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019 |archive-date=23 July 2019 |archive-url=https://web.archive.org/web/20190723142758/https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |url-status=live }}</ref><ref>{{cite conference |last1=Sah |first1=Chih-Tang |author1-link=Chih-Tang Sah |last2=Wanlass |first2=Frank |book-title=1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |title=Nanowatt logic using field-effect metal-oxide semiconductor triodes |author2-link=Frank Wanlass |date=February 1963 |volume=VI |pages=32–33 |doi=10.1109/ISSCC.1963.1157450}}</ref> CMOS was commercialised by [[RCA]] in the late 1960s.<ref name="computerhistory1963" /> RCA commercially used CMOS for its [[4000-series integrated circuits]] in 1968, starting with a 20{{nbsp}}μm process before gradually scaling to a [[10 μm process]] over the next several years.<ref name="Lojek330">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |page=330 |url=https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA330 |access-date=2019-07-21 |archive-date=2020-08-06 |archive-url=https://web.archive.org/web/20200806021239/https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA330 |url-status=live }}</ref> Many early semiconductor device manufacturers developed and built their own equipment such as ion implanters.<ref name="ion-implantation-in-silicon-technology">{{cite journal |url=https://www.axcelis.com/wp-content/uploads/2019/02/Ion_Implantation_in_Silicon_Technology.pdf |title=Ion Implantation in Silicon Technology |first1=Leonard |last1=Rubin |first2=John |last2=Poate |journal=The Industrial Physicist |volume=9 |issue=3 |date=June–July 2003 |publisher=[[American Institute of Physics]] |pages=12–15}}</ref>

In 1963, [[Harold M. Manasevit]] was the first to document epitaxial growth of [[silicon on sapphire]] while working at the [[Autonetics]] division of [[North American Aviation]] (now [[Boeing]]). In 1964, he published his findings with colleague William Simpson in the ''Journal of Applied Physics''.<ref name="Manasevit_1964">{{cite journal |last1=Manasevit |first1=H. M. |last2=Simpson |first2=W. J. |title=Single-Crystal Silicon on a Sapphire Substrate |journal=[[Journal of Applied Physics]] |year=1964 |volume=35 |issue=4 |pages=1349–51 |doi=10.1063/1.1713618|bibcode=1964JAP....35.1349M }}</ref> In 1965, C.W. Mueller and P.H. Robinson fabricated a MOSFET (metal–oxide–semiconductor field-effect transistor) using the silicon-on-sapphire process at [[RCA Laboratories]].<ref>{{cite journal |last1=Mueller |first1=C. W. |last2=Robinson |first2=P. H. |title=Grown-film silicon transistors on sapphire |journal=[[Proceedings of the IEEE]] |date=December 1964 |volume=52 |issue=12 |pages=1487–90 |doi=10.1109/PROC.1964.3436}}</ref>

Semiconductor device manufacturing has since spread from [[Texas]] and [[California]] in the 1960s to the rest of the world, including [[Asia]], [[Europe]], and the [[Middle East]]. 

Wafer size has grown over time, from 25&nbsp;mm (1 inch) in 1960, to 50&nbsp;mm (2 inches) in 1969, 100&nbsp;mm (4 inches) in 1976, 125&nbsp;mm (5 inches) in 1981, 150&nbsp;mm (6 inches) in 1983 and 200&nbsp;mm in 1992.<ref>{{cite book | url=https://books.google.com/books?id=NEkPEAAAQBAJ&dq=wafer+size+increase+over+time&pg=PA35 | isbn=978-1-351-24866-2 | title=Extending Moore's Law through Advanced Semiconductor Design and Processing Techniques | date=13 September 2018 | publisher=CRC Press }}</ref><ref>{{cite web | url=https://f450c.org/infographic/ | archive-url=https://web.archive.org/web/20151222155518/http://www.f450c.org/infographic/ | url-status=usurped | archive-date=December 22, 2015 | title=Evolution of the Silicon Wafer Infographic }}</ref>

In the era of 2-inch wafers, these were handled manually using tweezers and held manually for the time required for a given process. Tweezers were replaced by vacuum wands as they generate fewer particles<ref>{{cite book | url=https://books.google.com/books?id=iWTxDwAAQBAJ&dq=wafer+vacuum+wand&pg=PA148 | isbn=978-3-030-40021-7 | title=How Transistor Area Shrank by 1 Million Fold | date=15 July 2020 | publisher=Springer }}</ref> which can contaminate the wafers. Wafer carriers or cassettes, which can hold several wafers at once, were developed to carry several wafers between process steps, but wafers had to be individually removed from the carrier, processed and returned to the carrier, so acid-resistant carriers were developed to eliminate this time consuming process, so the entire cassette with wafers was dipped into wet etching and wet cleaning tanks. When wafer sizes increased to 100&nbsp;mm, the entire cassette would often not be dipped as uniformly, and the quality of the results across the wafer became hard to control. By the time 150&nbsp;mm wafers arrived, the cassettes were not dipped and were only used as wafer carriers and holders to store wafers, and robotics became prevalent for handling wafers. With 200&nbsp;mm wafers manual handling of wafer cassettes becomes risky as they are heavier.<ref>{{cite book | url=https://books.google.com/books?id=Md1-mZ69qMQC&dq=Wafer+box+cassette&pg=PA144 | isbn=978-0-7923-9619-2 | title=Wafer Fabrication: Factory Performance and Analysis | date=30 November 1995 | publisher=Springer }}</ref>

In the 1970s and 1980s, several companies migrated their semiconductor manufacturing technology from [[bipolar junction transistor|bipolar]] to MOSFET technology. Semiconductor manufacturing equipment has been considered costly since 1978.<ref>{{cite web | url=https://www.chiphistory.org/724-semiconductor-equipment-too-expensive-circa-1978 | title=Wafer fab costs skyrocketing out of control }}</ref><ref>https://ieeexplore.ieee.org/document/10569131</ref><ref>https://www.electronicdesign.com/technologies/power/article/21801160/igbts-or-mosfets-which-is-better-for-your-design</ref><ref>https://spectrum.ieee.org/the-future-of-transistors</ref>

In 1984, [[KLA Corporation|KLA]] developed the first automatic reticle and photomask inspection tool.<ref>{{cite web | url=https://www.chiphistory.org/682-kla-200-series-reticle-inspection-systems | title=Kla 200 Series }}</ref> In 1985, KLA developed an automatic inspection tool for silicon wafers, which replaced manual microscope inspection.<ref>{{cite web | url=https://www.chiphistory.org/235-kla-tencor-kla-2020 | title=KLA 2020 - the tool that sparked the yield management revolution }}</ref>

In 1985, SGS (now [[STmicroelectronics]]) invented BCD, also called [[BCDMOS]], a semiconductor manufacturing process using bipolar, CMOS and [[DMOS]] devices.<ref>{{Cite web|url=https://spectrum.ieee.org/three-chips-in-one-the-history-of-the-bcd-integrated-circuit|title=Three Chips in One: The History of the BCD Integrated Circuit - IEEE Spectrum|website=[[IEEE]]}}</ref> [[Applied Materials]] developed the first practical multi chamber, or cluster wafer processing tool, the Precision 5000.<ref>{{cite web | url=https://www.chiphistory.org/141-applied-materials-precision-5000-cvd | title=Applied Materials Precision 5000 CVD System }}</ref>

Until the 1980s, physical vapor deposition was the primary technique used for depositing materials onto wafers, until the advent of chemical vapor deposition.<ref>{{cite web | url=https://www.chiphistory.org/110-mrc-series-900-in-line-sputtering-system | title=Series 900 In-Line Sputtering System by MRC }}</ref> Equipment with diffusion pumps was replaced with those using turbomolecular pumps as the latter do not use oil which often contaminated wafers during processing in vacuum.<ref>{{cite book | url=https://books.google.com/books?id=i_brZUv8JEYC&dq=turbomolecular+pump+replaced+diffusion+pump&pg=PA72 | isbn=978-1-4377-7868-7 | title=Vacuum Deposition onto Webs, Films and Foils | date=21 June 2011 | publisher=William Andrew }}</ref>

200&nbsp;mm diameter wafers were first used in 1990 and became the standard until the introduction of 300&nbsp;mm diameter wafers in 2000.<ref>{{Cite conference|url=https://ieeexplore.ieee.org/document/993612|title=The world's first 300 mm fab at Infineon - challenges and success |book-title=Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) |doi=10.1109/ISSM.2000.993612 |s2cid=109383925 }}</ref><ref>{{cite web | url=https://www.edn.com/the-300mm-era-begins/ | title=The 300mm Era Begins | date=10 July 2000 }}</ref> Bridge tools were used in the transition from 150&nbsp;mm wafers to 200&nbsp;mm wafers<ref name="auto12">{{cite web | url=https://www.chiphistory.org/711-applied-materials-introduces-producer-wafer-fab-system | title=Applied Materials Producer }}</ref> and in the transition from 200&nbsp;mm to 300&nbsp;mm wafers.<ref>{{Cite web|url=http://www.chiphistory.org/878-300mm-semiconductor-wafers-get-a-reprieve|title=300mm Semiconductor Wafers get a reprieve|website=Chip History}}</ref><ref>{{cite web | url=https://www.eetimes.com/novellus-offers-300-mm-cvd-tool-thats-smaller-than-200-mm-lower-costs/ | title=Novellus offers 300-mm CVD tool that's smaller than 200-mm, lower costs | date=10 July 2000 }}</ref> The semiconductor industry has adopted larger wafers to cope with the increased demand for chips as larger wafers provide more surface area per wafer.<ref>{{cite conference|url=https://pubs.aip.org/aip/acp/article/449/1/97/975569/Model-based-silicon-wafer-criteria-for-optimal|title=Model-based silicon wafer criteria for optimal integrated circuit performance|first1=Howard R. |last1=Huff |first2=Randal K. |last2=Goodall |first3=W. Murray |last3=Bullis |first4=James A. |last4=Moreland |first5=Fritz G. |last5=Kirscht |first6=Syd R. |last6=Wilson |author7=The NTRS Starting Materials Team |book-title=AIP Conference Proceedings |volume=449 |issue=1 |pages=97–112 |date=24 November 1998 |doi=10.1063/1.56795}}</ref> Over time, the industry shifted to 300&nbsp;mm wafers which brought along the adoption of FOUPs,<ref name="auto11">{{cite book | url=https://books.google.com/books?id=3S-GDwAAQBAJ&dq=before+smif+wafers&pg=PT40 | title=Wafer Fabrication: Automatic Material Handling System | isbn=978-3-11-048723-7 | last1=Zhang | first1=Jie | date=24 September 2018 | publisher=Walter de Gruyter GmbH & Co KG }}</ref> but many products that are not advanced are still produced in 200&nbsp;mm wafers such as analog ICs, RF chips, power ICs, BCDMOS and [[MEMS]] devices.<ref>{{Cite web|url=https://semiengineering.com/200mm-fab-crunch/|title=200mm Fab Crunch|first=Mark|last=LaPedus|date=May 21, 2018|website=Semiconductor Engineering}}</ref> 

Some processes such as cleaning,<ref>{{cite web |url=https://www.eetimes.com/the-future-of-batch-and-single-wafer-processing-in-wafer-cleaning/ |title=The future of batch and single-wafer processing in wafer cleaning |first=Scott |last=Becker |date=24 March 2003 |website=[[EE Times]]}}</ref> ion implantation,<ref>{{cite conference | url=https://ieeexplore.ieee.org/document/586424 | title=Manufacturing advantages of single wafer high current ion implantation |book-title=Proceedings of 11th International Conference on Ion Implantation Technology | doi=10.1109/IIT.1996.586424 | s2cid=70599233 }}</ref><ref>{{cite journal | url=https://doi.org/10.1016/j.nimb.2005.05.016 | doi=10.1016/j.nimb.2005.05.016 | title=Approaches to single wafer high current ion implantation | date=2005 | last1=Renau | first1=A. | journal=Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms | volume=237 | issue=1–2 | pages=284–289 | bibcode=2005NIMPB.237..284R }}</ref> etching,<ref>{{cite book | url=https://books.google.com/books?id=xQ3yBwAAQBAJ&dq=batch+plasma+etching&pg=PA199 | isbn=978-1-4899-2566-4 | title=Dry Etching for VLSI | date=29 June 2013 | publisher=Springer }}</ref> annealing<ref>{{cite journal | url=https://link.springer.com/article/10.1557/PROC-470-201 | doi=10.1557/PROC-470-201 | title=Understanding the Impact of Batch vs. Single Wafer in Thermal Processing Using Cost of Ownership Analysis | date=1997 | last1=Hossain-Pas | first1=S. | last2=Pas | first2=M. F. | journal=MRS Proceedings | volume=470 }}</ref> and oxidation<ref>{{cite journal | url=https://ieeexplore.ieee.org/document/1198020 | title=Contrasting single-wafer and batch processing for memory devices |journal=IEEE Transactions on Semiconductor Manufacturing | date=2003 |volume=16 |issue=2 | doi=10.1109/TSM.2003.810939 | last1=Weimer | first1=R.A. | last2=Eppich | first2=D.M. | last3=Beaman | first3=K.L. | last4=Powell | first4=D.C. | last5=Gonzalez | first5=F. | pages=138–146 }}</ref> started to adopt single wafer processing instead of batch wafer processing in order to improve the reproducibility of results.<ref>{{cite book | url=https://books.google.com/books?id=TzL5aUslKDUC&dq=batch+single+wafer+etching&pg=PA309 | isbn=978-0-470-02056-2 | title=Introduction to Microfabrication | date=28 January 2005 | publisher=John Wiley & Sons }}</ref><ref>{{cite conference | url=https://ieeexplore.ieee.org/document/200629 | title=Trends in single-wafer processing |book-title=1992 Symposium on VLSI Technology Digest of Technical Papers | doi=10.1109/VLSIT.1992.200629 | s2cid=110840307 }}</ref> A similar trend existed in MEMS manufacturing.<ref>{{cite web | url=https://www.cmmmagazine.com/mems/single-wafer-vs-batch-wafer-processing-in-mems-manufacturing/ | title=Single Wafer vs Batch Wafer Processing in MEMS Manufacturing | date=2 August 2016 | access-date=18 February 2024 | archive-date=18 February 2024 | archive-url=https://web.archive.org/web/20240218221103/https://www.cmmmagazine.com/mems/single-wafer-vs-batch-wafer-processing-in-mems-manufacturing/ | url-status=dead }}</ref> In 1998, Applied Materials introduced the Producer, a cluster tool that had chambers grouped in pairs for processing wafers, which shared common vacuum and supply lines but were otherwise isolated, which was revolutionary at the time as it offered higher productivity than other cluster tools without sacrificing quality, due to the isolated chamber design.<ref>{{Cite web|url=http://www.chiphistory.org/712-applied-materials-producer-a-new-revolution-is-upon-us|title=Applied Materials Producer - a new revolution is upon us|website=Chip History}}</ref><ref name="auto12"/>