Editing Photolithography (section)

== Process ==
[[Image:Photolithography etching process.svg|thumb|140px|Simplified illustration of [[dry etching]] using positive photoresist during a photolithography process in semiconductor microfabrication (not to scale).]]
A single iteration of photolithography combines several steps in sequence. Modern cleanrooms use automated, [[industrial robot|robot]]ic wafer track systems to coordinate the process.<ref>{{cite book | url=https://books.google.com/books?id=FgDmEAAAQBAJ&dq=wafer+track&pg=PA1353 | isbn=978-981-99-2836-1 | title=Handbook of Integrated Circuit Industry | date=27 November 2023 | publisher=Springer }}</ref> The procedure described here omits some advanced treatments, such as thinning agents.<ref>{{cite book |last=Jaeger |first=Richard C. |title=Introduction to Microelectronic Fabrication |edition=2nd |year=2002 |publisher=Prentice Hall |location=Upper Saddle River |isbn=978-0-201-44494-0 |chapter=Lithography}}</ref> The photolithography process is carried out by the wafer track and stepper/scanner, and the wafer track system and the stepper/scanner are installed side by side. Wafer track systems are also known as wafer coater/developer systems, which perform the same functions.<ref>{{cite book | chapter-url=https://www.spiedigitallibrary.org/conference-proceedings-of-spie/9425/94251A/Coaterdeveloper-process-integration-of-metal-oxide-based-photoresist/10.1117/12.2085982.short | doi=10.1117/12.2085982 | chapter=Coater/Developer process integration of metal-oxide based photoresist | title=Advances in Patterning Materials and Processes XXXII | date=2015 | editor-last1=Wallow | editor-last2=Hohle | editor-first1=Thomas I. | editor-first2=Christoph K. | last1=Clark | first1=Benjamin L. | last2=Kocsis | first2=Michael | last3=Greer | first3=Michael | last4=Grenville | first4=Andrew | last5=Saito | first5=Takashi | last6=Huli | first6=Lior | last7=Farrell | first7=Richard | last8=Hetzer | first8=David | last9=Hu | first9=Shan | last10=Matsumoto | first10=Hiroie | last11=Metz | first11=Andrew | last12=Kawakami | first12=Shinchiro | last13=Matsunaga | first13=Koichi | last14=Enomoto | first14=Masashi | last15=Lauerhaas | first15=Jeffrey | last16=Ratkovich | first16=Anthony | last17=Dekraker | first17=David | volume=9425 | pages=355–361 | s2cid=122169514 }}</ref><ref name="Handbook of VLSI Microlithography">{{cite book | url=https://books.google.com/books?id=kPIpg6plqnYC&dq=wafer+track&pg=PA254 | isbn=9780080946801 | title=Handbook of VLSI Microlithography, 2nd Edition | date=April 2001 | publisher=Cambridge University Press }}</ref> Wafer tracks are named after the "tracks" used to carry wafers inside the machine,<ref>{{cite book | url=https://books.google.com/books?id=BmRmyt-k1BoC&dq=wafer+track&pg=PA52 | isbn=9781566770040 | title=Proceedings of the Seventh Symposium on Automated Integrated Circuits Manufacturing | date=1992 | publisher=The Electrochemical Society }}</ref> but modern machines do not use tracks.<ref name="Handbook of VLSI Microlithography"/>

=== Cleaning ===
If organic or inorganic contaminations are present on the wafer surface, they are usually removed by wet chemical treatment, e.g. the [[RCA clean]] procedure based on solutions containing [[hydrogen peroxide]]. Other solutions made with trichloroethylene, acetone or methanol can also be used to clean.<ref>{{Cite journal| title = Reactions of thin metal films with crystalline and amorphous Al2O3| year = 1986| last1 = Zhao| first1 = X-A| last2 = Kolawa| first2 = E| last3 = Nicolet| first3 = M-A| journal = Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films| volume = 4| issue = 6| page = 3139| doi = 10.1116/1.573642| bibcode = 1986JVSTA...4.3139Z| url = https://authors.library.caltech.edu/10832/}}</ref>

=== Preparation ===
The wafer is initially heated to a temperature sufficient to drive off any moisture that may be present on the wafer surface; 150&nbsp;°C for ten minutes is sufficient. Wafers that have been in storage must be chemically cleaned to remove [[contamination]]. A [[liquid]] or [[gas]]eous "adhesion promoter", such as [[Bis(trimethylsilyl)amine|Bis(trimethylsilyl)amine ("hexamethyldisilazane", HMDS)]], is applied to promote adhesion of the photoresist to the wafer.  The surface layer of silicon dioxide on the wafer reacts with HMDS to form tri-methylated silicon-dioxide, a highly water repellent layer not unlike the layer of wax on a car's paint. This water repellent layer prevents the aqueous developer from penetrating between the photoresist layer and the wafer's surface, thus preventing so-called lifting of small photoresist structures in the (developing) pattern. In order to ensure the development of the image, it is best covered and placed over a hot plate and let it dry while stabilizing the temperature at 120&nbsp;°C.<ref>{{cite web | title=Semiconductor Lithography (Photolithography) - The Basic Process | url=http://www.lithoguru.com/scientist/lithobasics.html}}</ref>

=== Photoresist application ===
The wafer is covered with [[photoresist]] liquid by [[spin coating]]. Thus, the top layer of resist is quickly ejected from the wafer's edge while the bottom layer still creeps slowly radially along the wafer. In this way, any 'bump' or 'ridge' of resist is removed, leaving a very flat layer. However, viscous films may result in large edge beads which are areas at the edges of the wafer or photomask<ref>{{Cite book|chapter-url=https://www.spiedigitallibrary.org/conference-proceedings-of-spie/6283/62831P/The-design-and-qualification-of-the-TEL-CLEAN-TRACK-ACT/10.1117/12.681751.full|title=Photomask and Next-Generation Lithography Mask Technology XIII|first1=Andrew|last1=Jamieson|first2=Thuc|last2=Dam|first3=Ki-Ho|last3=Baik|first4=Ken|last4=Duerksen|first5=Elie|last5=Eidson|first6=Keiji|last6=Akai|first7=Kazuya|last7=Hisano|first8=Norifumi|last8=Kohama|first9=Shinichi|last9=Machidori|editor-first1=Morihisa |editor-last1=Hoga |chapter=The design and qualification of the TEL CLEAN TRACK ACT M photomask coating tool at Intel |date=May 20, 2006|publisher=SPIE|volume=6283|pages=471–478|via=www.spiedigitallibrary.org|doi=10.1117/12.681751|s2cid=110358910 }}</ref> with increased resist thickness whose planarization has physical limits.<ref>{{cite journal |last=Arscott |first=Steve |date=8 January 2020 |title=The limits of edge bead planarization and surface levelling in spin-coated liquid films |url=https://iopscience.iop.org/article/10.1088/1361-6439/ab60be/meta |journal=Journal of Micromechanics and Microengineering |volume=30 |issue=2 |pages=025003 |doi=10.1088/1361-6439/ab60be |s2cid=214580612 |hdl-access=free |hdl=20.500.12210/44092}}</ref> Often, Edge bead removal (EBR) is carried out, usually with a nozzle, to remove this extra resist as it could otherwise cause particulate contamination.<ref>{{cite book | url=https://books.google.com/books?id=FgDmEAAAQBAJ&dq=photoresist+edge+bead+removal&pg=PA1439 | isbn=978-981-99-2836-1 | title=Handbook of Integrated Circuit Industry | date=27 November 2023 | publisher=Springer }}</ref><ref>{{Cite journal|url=https://ieeexplore.ieee.org/document/9624953|title=An Investigation of Edge Bead Removal Width Variability, Effects and Process Control in Photolithographic Manufacturing |doi=10.1109/TSM.2021.3129770 |s2cid=244560651 |date=2022 |last1=Reiter |first1=Tamas |last2=McCann |first2=Michael |last3=Connolly |first3=James |last4=Haughey |first4=Sean |journal=IEEE Transactions on Semiconductor Manufacturing |volume=35 |pages=60–66 }}</ref><ref>{{Cite book|chapter-url=https://www.spiedigitallibrary.org/ebooks/PM/Advanced-Processes-for-193-nm-Immersion-Lithography/2/Process-Steps-in-the-Track/10.1117/3.820233.ch2|chapter=Process Steps in the Track|first1=Yayi|last1=Wei|first2=Robert|last2=Brainard|title=Advanced Processes for 193-nm Immersion Lithography |date=February 19, 2009|volume=PM189|pages=19–52|via=www.spiedigitallibrary.org|doi=10.1117/3.820233.ch2|isbn=978-0-8194-7557-2 }}</ref>
Final thickness is also determined by the evaporation of liquid solvents from the resist. For very small, dense features (< 125 or so nm), lower resist thicknesses (< 0.5 microns) are needed to overcome collapse effects at high aspect ratios; typical aspect ratios are < 4:1.

The photoresist-coated wafer is then prebaked to drive off excess photoresist solvent, typically at 90 to 100&nbsp;°C for 30 to 60 seconds on a hotplate.<!--ref for hotplate--><ref>{{Cite book|url=https://books.google.com/books?id=FgDmEAAAQBAJ&dq=photoresist+bake+300mm&pg=PA1357|title=Handbook of Integrated Circuit Industry|first1=Yangyuan|last1=Wang|first2=Min-Hwa|last2=Chi|first3=Jesse Jen-Chung|last3=Lou|first4=Chun-Zhang|last4=Chen|date=November 27, 2023|publisher=Springer Nature|isbn=978-981-99-2836-1 |via=Google Books}}</ref> A BARC coating (Bottom Anti-Reflectant Coating) may be applied before the photoresist is applied, to avoid reflections from occurring under the photoresist and to improve the photoresist's performance at smaller semiconductor nodes such as 45&nbsp;nm and below.<ref>{{cite book | url=https://books.google.com/books?id=_hTLDCeIYxoC&dq=bottom+anti+reflective+coating&pg=PA647 | isbn=9781420051537 | title=Microlithography: Science and Technology, Second Edition | date=3 October 2018 | publisher=CRC Press }}</ref><ref>{{cite book | chapter-url=https://www.spiedigitallibrary.org/conference-proceedings-of-spie/6519/651928/BARC-bottom-anti-reflective-coating-for-immersion-process/10.1117/12.711305.short | doi=10.1117/12.711305 | chapter=BARC (Bottom anti-reflective coating) for immersion process | title=Advances in Resist Materials and Processing Technology XXIV | date=2007 | editor-last1=Lin | editor-first1=Qinghuang | last1=Hiroi | first1=Yoshiomi | last2=Kishioka | first2=Takahiro | last3=Sakamoto | first3=Rikimaru | last4=Maruyama | first4=Daisuke | last5=Ohashi | first5=Takuya | last6=Ishida | first6=Tomohisa | last7=Kimura | first7=Shigeo | last8=Sakaida | first8=Yasushi | last9=Watanabe | first9=Hisayuki | volume=6519 | pages=731–740 | s2cid=122377285 }}</ref><ref name="Wakamizu-2008">{{cite book | chapter-url=https://www.spiedigitallibrary.org/conference-proceedings-of-spie/7140/1/193-nm-immersion-lithography-for-high-volume-manufacturing-using-novel/10.1117/12.804675.short | doi=10.1117/12.804675 | chapter=193-nm immersion lithography for high volume manufacturing using novel immersion exposure tool and coater/Developer system | title=Lithography Asia 2008 | date=2008 | editor-last1=Chen | editor-first1=Alek C. | last1=Wakamizu | first1=Shinya | last2=Kyouda | first2=Hideharu | last3=Nakano | first3=Katsushi | last4=Fujiwara | first4=Tomoharu | volume=7140 | pages=819–826 | s2cid=109584069 | editor-first2=Burn | editor-first3=Anthony | editor-last2=Lin | editor-last3=Yen }}</ref> Top Anti-Reflectant Coatings (TARCs) also exist.<ref>{{Cite book|url=https://books.google.com/books?id=Sx39H8XR1FcC&dq=Advanced+Processes+for+193-nm+Immersion+Lithography&pg=PR13|title=Advanced Processes for 193-nm Immersion Lithography|first1=Yayi|last1=Wei|first2=Robert L.|last2=Brainard|date=January 1, 2009|publisher=SPIE Press|isbn=978-0-8194-7557-2 |via=Google Books}}</ref> EUV lithography is unique in the sense it allows for the use of photoresists with metal oxides.<ref>{{cite web | url=https://semiwiki.com/semiconductor-manufacturers/intel/300316-resist-development-for-high-na-euv/ | title=Resist Development for High-NA EUV - Read more on SemiWiki | date=25 February 2024 }}</ref>

=== Exposure and developing ===
After prebaking, the photoresist is exposed to a pattern of intense light. The exposure to light causes a chemical change that allows some of the photoresist to be removed by a special solution, called "developer" by analogy with [[photographic developer]].  Positive photoresist, the most common type, becomes soluble in the developer when exposed; with negative photoresist, unexposed regions are soluble in the developer.

A post-exposure bake (PEB) is performed before developing, typically to help reduce [[standing wave]] phenomena caused by the destructive and constructive [[Interference (wave propagation)|interference]] patterns of the incident light. In deep ultraviolet lithography, chemically amplified resist (CAR) chemistry is used. This resist is much more sensitive to PEB time, temperature, and delay, as the resist works by creating acid when it is hit by photons, and then undergoes an "exposure" reaction (creating acid, making the polymer soluble in the basic developer, and performing a chemical reaction catalyzed by acid) which mostly occurs in the PEB.<ref>{{cite web | first=Omkaram | last=Nalamasu | title=An Overview of Resist Processing for DUV Photolithography | url=https://www.jstage.jst.go.jp/article/photopolymer1988/4/3/4_3_299/_pdf | display-authors=etal }}</ref><ref>{{Cite web|url=https://semiengineering.com/euvs-new-problem-areas/|title=EUV's New Problem Areas|first=Mark|last=LaPedus|date=March 19, 2018|website=Semiconductor Engineering}}</ref>

The develop chemistry is delivered on a spinner, much like photoresist. Developers originally often contained [[sodium hydroxide]] (NaOH). However, [[sodium]] is considered an extremely undesirable contaminant in [[MOSFET]] fabrication because it degrades the [[Electrical insulation|insulating]] properties of gate oxides (specifically, sodium ions can migrate in and out of the gate, changing the threshold voltage of the transistor and making it harder or easier to turn the transistor on over time). Metal-ion-free developers such as [[tetramethylammonium hydroxide]] (TMAH) are now used. The temperature of the developer might be tightly controlled using jacketed (dual walled) hoses to within 0.2&nbsp;°C.<ref name="Levinson-2005"/> The nozzle that coats the wafer with developer may influence the amount of developer that is necessary.<ref>{{cite book | s2cid=54991701 | doi=10.2991/ICMRA-15.2015.256 | chapter=A summary of the current development of developing technology in the field of integrated circuit manufacturing | title=Proceedings of the 3rd International Conference on Mechatronics, Robotics and Automation | date=2015 | last1=Wang | first1=Han | last2=Ning | first2=Feng | last3=Xu | first3=Qiang | last4=Liu | first4=Xue-Ping | volume=15 | isbn=978-94-62520-76-9 }}</ref><ref name="Handbook of VLSI Microlithography"/>

The resulting wafer is then "hard-baked" if a non-chemically amplified resist was used, typically at 120 to 180&nbsp;°C<ref>{{Cite web|url=https://cores.research.asu.edu/nanofabrication-and-cleanroom/techniques-lithography|title=Techniques - lithography {{!}} Core Facilities|website=cores.research.asu.edu|access-date=2020-02-04}}</ref> for 20 to 30 minutes. The hard bake solidifies the remaining photoresist, to make a more durable protecting layer in future [[ion implantation]], [[Chemical milling|wet chemical etching]], or [[plasma etching]].

From preparation until this step, the photolithography procedure has been carried out by two machines: the photolithography stepper or scanner, and the coater/developer. The two machines are usually installed side by side, and are "linked" together.<ref>{{cite book | chapter-url=https://www.spiedigitallibrary.org/conference-proceedings-of-spie/6154/61544L/Wafer-management-between-coatdeveloper-track-and-immersion-lithography-tool/10.1117/12.656303.short | doi=10.1117/12.656303 | chapter=Wafer management between coat/Developer track and immersion lithography tool | title=Optical Microlithography XIX | date=2006 | editor-last1=Flagello | editor-first1=Donis G. | last1=Fujiwara | first1=Tomoharu | last2=Shiraishi | first2=Kenichi | last3=Tanizaki | first3=Hirokazu | last4=Ishii | first4=Yuuki | last5=Kyoda | first5=Hideharu | last6=Yamamoto | first6=Taro | last7=Ishida | first7=Seiki | volume=6154 | pages=1553–1562 | s2cid=110508653 }}</ref><ref name="Wakamizu-2008"/><ref>{{cite book | url=https://books.google.com/books?id=Sx39H8XR1FcC&dq=photolithography+track+system&pg=PA2 | isbn=9780819475572 | title=Advanced Processes for 193-nm Immersion Lithography | date=2009 | publisher=SPIE Press }}</ref>

=== Etching, implantation ===
{{Main|Etching (microfabrication)}}

In etching, a liquid ("wet") or [[plasma (physics)|plasma]] ("dry") chemical agent removes the uppermost layer of the substrate in the areas that are not protected by photoresist. In [[semiconductor fabrication]], [[dry etching]] techniques are generally used, as they can be made [[anisotropic]], in order to avoid significant undercutting of the photoresist pattern. This is essential when the width of the features to be defined is similar to or less than the thickness of the material being etched (i.e. when the aspect ratio approaches unity). Wet etch processes are generally isotropic in nature, which is often indispensable for [[microelectromechanical systems]], where suspended structures must be "released" from the underlying layer.

The development of low-defectivity anisotropic dry-etch process has enabled the ever-smaller features defined photolithographically in the resist to be transferred to the substrate material.

=== Photoresist removal ===
After a photoresist is no longer needed, it must be removed from the substrate. This usually requires a liquid "resist stripper", which chemically alters the resist so that it no longer adheres to the substrate. Alternatively, the photoresist may be removed by a plasma containing [[oxygen]], which oxidizes it. This process is called [[plasma ashing]] and resembles dry etching. The use of [[N-Methyl-2-pyrrolidone|1-Methyl-2-pyrrolidone (NMP)]] solvent for photoresist is another method used to remove an image. When the resist has been dissolved,  the solvent can be removed by heating to 80&nbsp;°C without leaving any residue.<ref>{{cite web | title=AN-Methyl-2-Pyrrolidone | url=http://www.lyondellbasell.com/techlit/techlit/2313.pdf}}</ref>