Editing Peripheral Component Interconnect (section)

==Interrupts==
Devices are required to follow a protocol so that the [[interrupt request|interrupt-request]] (IRQ) lines can be shared. The PCI bus includes four interrupt lines, INTA# through INTD#, all of which are available to each device. Up to eight PCI devices share the same IRQ line (INTINA# through INTINH#) in [[Advanced Programmable Interrupt Controller|APIC]]-enabled x86 systems. Interrupt lines are not wired in parallel as are the other PCI bus lines. The positions of the interrupt lines rotate between slots, so what appears to one device as the INTA# line is INTB# to the next and INTC# to the one after that. Single-function devices usually use their INTA# for interrupt signaling, so the device load is spread fairly evenly across the four available interrupt lines. This alleviates a common problem with sharing interrupts.

The mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is implementation-dependent. Platform-specific [[firmware]] or operating system code is meant to know this, and set the "interrupt line" field in each device's configuration space indicating which IRQ it is connected to.

PCI interrupt lines are [[interrupt#Level-triggered|level-triggered]]. This was chosen over [[Interrupt#Edge-triggered|edge-triggering]] to gain an advantage when servicing a shared interrupt line, and for robustness: edge-triggered interrupts are easy to miss.

Later revisions of the PCI specification add support for [[Message Signaled Interrupts|message-signaled interrupts]]. In this system, a device signals its need for service by performing a memory write, rather than by asserting a dedicated line. This alleviates the problem of scarcity of interrupt lines. Even if interrupt vectors are still shared, it does not suffer the sharing problems of level-triggered interrupts. It also resolves the routing problem, because the memory write is not unpredictably modified between device and host. Finally, because the message [[In-band signaling|signaling is in-band]], it resolves some synchronization problems that can occur with posted writes and [[Out-of-band data|out-of-band]] interrupt lines.

[[PCI Express]] does not have physical interrupt lines at all. It uses message-signaled interrupts exclusively.