Editing Pentium (original) (section)

==Development==
The P5 microarchitecture was designed by the same Santa Clara team which designed the 386 and 486.<ref>{{cite book |page=1 |title=The Pentium Chronicles: The People, Passion, and Politics Behind Intel's Landmark Chips |first=Robert P. |last=Colwell |author-link=Bob Colwell |publisher=Wiley |date=2006 |isbn=978-0-471-73617-2}}</ref> Design work started in 1989;<ref name="inside-intel">{{cite magazine |title=Inside Intel |magazine=[[Business Week]] |issue=3268 |date=June 1, 1992}}</ref>{{rp|page=88}} the team decided to use a [[superscalar]] RISC architecture which would be a convergence of RISC and CISC technology,<ref>House, Dave, "Putting the RISC vs. CISC Debate to Rest", Intel Corporation, Microcomputer Solutions, November/December 1991, page 18</ref> with on-chip cache, floating-point, and branch prediction. The preliminary design was first successfully simulated in 1990, followed by the [[Integrated circuit layout|laying-out]] of the design. By this time, the team had several dozen engineers. The design was [[tape-out|taped out]], or transferred to silicon, in April 1992, at which point beta-testing began.<ref>{{cite magazine |url=http://www.iptegrity.com/index.php?option=com_content&task=view&id=34&Itemid=42 |title=The hot new star of microchips |first=Monica |last=Horten |magazine=[[New Scientist]] |issue=1871 |pages=31 ff |date=May 1, 1993 |access-date=June 9, 2009 |archive-url=https://web.archive.org/web/20110727064516/http://www.iptegrity.com/index.php?option=com_content&task=view&id=34&Itemid=42 |archive-date=July 27, 2011 |url-status=dead}}</ref> By mid-1992, the P5 team had 200 engineers.<ref name="inside-intel" />{{rp|page=89}} Intel at first planned to demonstrate the P5 in June 1992 at the trade show [[PC Expo]], and to formally announce the processor in September 1992,<ref>{{cite magazine | page     = 8| title    = Intel to offer a peek at its '586' chip| first    = Tom | last     = Quinlan| magazine = [[InfoWorld]]| date     = 16 March 1992| url      = {{ google books | id=3D0EAAAAMBAJ | page=8 |plain-url=true }}}}</ref> but design problems forced the demo to be cancelled, and the official introduction of the chip was delayed until the spring of 1993.<ref>{{cite magazine| page     = 1| title    = Design woes force Intel to cancel 586 chip demo| first1   = Tom| last1    = Quinlan| first2   = Cate | last2    = Corcoran| magazine = [[InfoWorld]]| volume   = 14| issue    = 24| date     = 15 June 1992| url      = {{ google books | id=aVEEAAAAMBAJ | page=1 |plain-url=true }}}}</ref><ref>{{cite magazine | pages     = 1, 103| title    = P5 chip delay won't alter rivals' plans| first1   = Tom | last1    = Quinlan| first2   = Cate| last2    = Corcoran| magazine = [[InfoWorld]]| volume   = 14| issue    = 30| date     = 27 July 1992| url      = {{ google books | id=HVEEAAAAMBAJ | page=1  |plain-url=true }}}}</ref>

[[John H. Crawford]], chief architect of the original 386, co-managed the design of the P5,<ref>{{cite magazine| url      = {{ google books | id=ajkEAAAAMBAJ |page = 51 | plain-url=true }}| pages     = 51–55| title    = Intel Turns 35: Now What?| first    = David L. | last     = Margulius| magazine = [[InfoWorld]]| date     = July 21, 2003| volume   = 25| issue    = 28| issn     = 0199-6649}}</ref> along with [[Donald Alpert]], who managed the architectural team. Dror Avnon managed the design of the FPU.<ref>{{cite magazine |page=21 |url=https://ieeexplore.ieee.org/document/216745 |title=Architecture of the Pentium microprocessor] |first1=D. |last1=Alpert |first2=D. |last2=Avnon |magazine=[[IEEE Micro]] |volume=13 |issue=3 |date=June 1993 |doi=10.1109/40.216745}}</ref> [[Vinod K. Dham]] was general manager of the P5 group.<ref name="inside-intel" />{{rp|page=90}}

Intel's [[Larrabee (microarchitecture)|Larrabee]] multicore architecture project uses a processor core derived from a P5 core (P54C), augmented by [[Multithreading (computer architecture)|multithreading]], [[Intel 64|64-bit instructions]], and a 16-byte wide [[Vector processor|vector processing unit]].<ref>§3 of {{cite journal |first1=L. |last1=Seiler |first2=D. |last2=Cavin |first3=E. |last3=Espasa |first4=T. |last4=Grochowski |first5=M. |last5=Juan |first6=P. |last6=Hanrahan |first7=S. |last7=Carmean |first8=A. |last8=Sprangle |first9=J. |last9=Forsyth |first10=R. |last10=Abrash |first11=R. |last11=Dubey |first12=E. |last12=Junkins |first13=T. |last13=Lake |first14=P. |last14=Sugerman |date=August 2008 |title=Larrabee: A Many-Core x86 Architecture for Visual Computing |journal=[[ACM Transactions on Graphics]] |volume=27 |issue=3 |pages=18:11 |issn=0730-0301 |doi=10.1145/1360612.1360617 |url=https://pages.cs.wisc.edu/~markhill/restricted/siggraph08_larrabee.pdf |access-date=August 18, 2023 |series=Proceedings of ACM SIGGRAPH 2008 |s2cid=52799248 }}</ref> Intel's low-powered [[Bonnell (microarchitecture)|Bonnell microarchitecture]] employed in early [[Intel Atom|Atom]] processor cores also uses an in-order dual pipeline similar to P5.<ref>{{Citation |title=Why Pine Trail Isn't Much Faster Than the First Atom |last=Shimpi |first=Anand Lal |date=January 27, 2010 |url=http://www.anandtech.com/show/2925 |access-date=August 4, 2010}}</ref>

Intel used the Pentium name instead of 586, because in 1991, it had lost a trademark dispute over the "386" trademark, when a judge ruled that the number was [[generic trademark|generic]]. The company hired [[Lexicon Branding]] to come up with a new, non-numeric name.<ref>{{cite news |last1=Smith |first1=Ernie |title=Why Intel Couldn't Trademark Numbers Anymore |url=https://www.vice.com/en/article/why-intel-couldnt-trademark-numbers-anymore/ |access-date=July 13, 2023 |work=Vice |date=June 14, 2017 |language=en}}</ref>

===Improvements over the i486===
The P5 microarchitecture brings several important advances over the prior i486 architecture.

* ''Performance'':
** [[Superscalar]] architecture – The Pentium has two datapaths (pipelines) that allow it to complete two instructions per clock cycle in many cases. The main pipe (U) can handle any instruction, while the other (V) can handle the most common simple instructions. Some{{who|date=July 2018}} [[reduced instruction set computer]] (RISC) proponents had argued that the "complicated" x86 instruction set would probably never be implemented by a tightly pipelined [[microarchitecture]], much less by a dual-pipeline design. The 486 and the Pentium demonstrated that this was indeed possible and feasible.
** [[64-bit]] external databus doubles the amount of information possible to read or write on each memory access and therefore allows the Pentium to load its code cache faster than the 80486; it also allows faster access and storage of 64-bit and 80-bit [[x87]] [[Floating-point unit|FPU]] data.
** Separation of code and data caches lessens the fetch and operand read/write conflicts compared to the 486. To reduce access time and implementation cost, both of them are [[Set-associative|2-way associative]], instead of the single 4-way cache of the 486. A related enhancement in the Pentium is the ability to read a contiguous block from the code cache even when it is split between two cache lines (at least 17 bytes in worst case).
** Much faster [[floating-point unit]]. Some instructions showed an enormous improvement, most notably FMUL, with up to 15 times higher throughput than in the 80486 FPU. The Pentium is also able to execute a FXCH ST(x) instruction in parallel with an ordinary (arithmetical or load/store) FPU instruction.
** Four-input address adders enables the Pentium to further reduce the address calculation latency compared to the 80486. The Pentium can calculate full addressing modes with ''segment-base'' + ''base-register'' + ''scaled register'' + ''immediate offset'' in a single cycle; the 486 has a three-input address adder only, and must therefore divide such calculations between two cycles.
** The [[microcode]] can employ both pipelines to enable auto-repeating instructions such as REP MOVSW perform one iteration every clock cycle, while the [[80486]] needed three clocks per iteration (and the earliest x86 chips significantly more than the 486). Also, optimization of the access to the first microcode words during the decode stages helps in making several frequent instructions execute significantly more quickly, especially in their most common forms and in typical cases. Some examples are (486→Pentium, in clock cycles): CALL (3→1), RET (5→2), shifts/rotates (2–3→1).
** A faster, fully hardware-based multiplier makes instructions such as MUL and IMUL several times faster (and more predictable) than in the 80486; the execution time is reduced from 13 to 42 clock cycles down to 10–11 for 32-bit operands.
** Virtualized interrupt to speed up [[virtual 8086 mode]].
** Branch prediction
* ''Other features'':
** Enhanced debug features with the introduction of the Processor-based debug port (see ''Pentium Processor Debugging'' in the Developers Manual, Vol 1).
** Enhanced self-test features like the L1 cache parity check (see ''Cache Structure'' in the Developers Manual, Vol 1).
** New instructions: CPUID, CMPXCHG8B, RDTSC, RDMSR, WRMSR, RSM.
** Test registers TR0–TR7 and MOV instructions for access to them were eliminated.
* The later Pentium MMX also added the [[MMX (instruction set)|MMX instruction set]], a basic integer ''single instruction, multiple data'' ([[SIMD]]) instruction set extension marketed for use in [[multimedia]] applications. MMX could not be used simultaneously with the [[x87]] FPU instructions because the registers were reused (to allow fast context switches). More important enhancements were the doubling of the instruction and data cache sizes and a few microarchitectural changes for better performance.

The Pentium was designed to execute over 100&nbsp;million [[instructions per second]] (MIPS),<ref>{{cite web |url=http://dede.essortment.com/pcusersguides_rjje.htm |title=PC users guide: General Computer Information |access-date=September 14, 2007 |url-status=dead |archive-url=https://web.archive.org/web/20070728013256/http://dede.essortment.com/pcusersguides_rjje.htm |archive-date=July 28, 2007}}</ref> and the 75&nbsp;MHz model was able to reach 126.5 MIPS in certain benchmarks.<ref>{{cite web|url=http://www.islandnet.com/~kpolsson/micropro/proc1994.htm |title=Chronology of Microprocessors |first=Ken |last=Polsson}}</ref> The Pentium architecture typically offered just under twice the performance of a 486 processor per clock cycle in common benchmarks. The fastest 80486 parts (with slightly improved microarchitecture and 100&nbsp;MHz operation) were almost as powerful as the first-generation Pentiums, and the [[AMD]] [[Am5x86]], which despite its name is actually a 486-class CPU, was roughly equal to the Pentium 75 regarding pure ALU performance.

===Errata===
The early versions of 60–66&nbsp;MHz P5 Pentiums had a problem in the floating-point unit that resulted in incorrect (but predictable) results from some division operations. This flaw, discovered in 1994 by professor Thomas Nicely at Lynchburg College, Virginia, became widely known as the [[Pentium FDIV bug]] and caused embarrassment for Intel, which created an exchange program to replace the faulty processors.

In 1997, another erratum was discovered that could allow a malicious program to crash a system without any special privileges, the "[[Pentium F00F bug|F00F bug]]". All P5 series processors were affected and no fixed steppings were ever released, however contemporary operating systems were patched with workarounds to prevent crashes.