Editing PCI Express (section)

=== Lane <span class="anchor" id="LANE"></span> ===
A lane is composed of two [[differential signaling]] pairs, with one pair for receiving data and the other for transmitting. Thus, each lane is composed of four wires or [[signal trace]]s. Conceptually, each lane is used as a [[full-duplex]] [[byte stream]], transporting data packets in eight-bit "byte" format simultaneously in both directions between endpoints of a link.<ref name="2Nt8T" /> Physical PCI Express links may contain 1, 4, 8 or 16 lanes.<ref name="Gchhw" /><ref name="pcie-basics" />{{rp|4,5}}<ref name="faq1" /> Lane counts are written with an "x" prefix (for example, "x8" represents an eight-lane card or slot), with x16 being the largest size in common use.<ref name="odC7t" /> Lane sizes are also referred to via the terms "width" or "by" e.g., an eight-lane slot could be referred to as a "by 8" or as "8 lanes wide."

For mechanical card sizes, see [[#Form factors|below]].