Editing Opteron (section)

===Multi-processor features===
In multi-processor systems (more than one Opteron on a single [[motherboard]]), the [[Central processing unit|CPUs]] communicate using the [[Direct Connect Architecture]] over high-speed [[HyperTransport]] links. Each CPU can access the main memory of another processor, transparent to the programmer. The Opteron approach to multi-processing is not the same as standard [[symmetric multiprocessing]]; instead of having one bank of memory for all CPUs, each CPU has its own memory. Thus the Opteron is a [[Non-Uniform Memory Access]] (NUMA) architecture. The Opteron CPU directly supports up to an 8-way configuration, which can be found in mid-level servers. Enterprise-level servers use additional (and expensive) routing chips to support more than 8 CPUs per box.

In a variety of computing benchmarks, the Opteron architecture has demonstrated better multi-processor scaling than the Intel [[Xeon]]<ref>{{cite web | title=SPECint2006 Rate Results for multiprocessor systems | url=http://www.spec.org/cgi-bin/osgresults | access-date = December 27, 2008 }}</ref> which did not have a point to point system until QPI and integrated memory controllers with the Nehalem design. This is primarily because adding another Opteron processor increases memory bandwidth, while that is not always the case for Xeon systems, and the fact that the Opterons use a [[switched fabric]], rather than a shared [[bus (computing)|bus]]. In particular, the Opteron's integrated memory controller allows the CPU to access local [[Random-access memory|RAM]] very quickly.  In contrast, multiprocessor Xeon system CPUs share only two common buses for both processor-processor and processor-memory communication. As the number of CPUs increases in a typical Xeon system, [[bus contention|contention]] for the shared bus causes computing efficiency to drop. Intel migrated to a memory architecture similar to the Opteron's for the [[Intel Core i7]] family of processors and their Xeon derivatives.