Editing Non-uniform memory access (section)

=={{Anchor|CCNUMA}}Cache coherent NUMA (ccNUMA)==
[[Image:Hwloc.png|right|300px|thumb|Topology of a ccNUMA [[Bulldozer (microarchitecture)|Bulldozer]] server extracted using hwloc's lstopo tool.]]

{{details|Directory-based cache coherence}}

Nearly all CPU architectures use a small amount of very fast non-shared memory known as [[CPU cache|cache]] to exploit [[locality of reference]] in memory accesses. With NUMA, maintaining [[cache coherence]] across shared memory has a significant overhead. Although simpler to design and build, non-cache-coherent NUMA systems become prohibitively complex to program in the standard [[von Neumann architecture]] programming model.<ref>{{Cite web
 | url = http://www.slideshare.net/networksguy/ccnuma-cache-coherent-nonuniform-memory-access
 | title = ccNUMA: Cache Coherent Non-Uniform Memory Access
 | year = 2014 | access-date = 2014-01-27
 | publisher = slideshare.net
}}</ref>

Typically, ccNUMA uses inter-processor communication between cache controllers to keep a consistent memory image when more than one cache stores the same memory location. For this reason, ccNUMA may perform poorly when multiple processors attempt to access the same memory area in rapid succession.  Support for NUMA in [[operating system]]s attempts to reduce the frequency of this kind of access by allocating processors and memory in NUMA-friendly ways and by avoiding scheduling and locking algorithms that make NUMA-unfriendly accesses necessary.<ref>{{Cite web
 | url = http://www.cs.berkeley.edu/~kubitron/cs258/handouts/papers/p80-stenstrom.pdf
 | title = Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures
 | year = 2002 | access-date = 2014-01-27
 | author1 = Per Stenstromt | author2 = Truman Joe | author3 = Anoop Gupta
 | publisher = ACM }}</ref>

Alternatively, cache coherency protocols such as the [[MESIF protocol]] attempt to reduce the communication required to maintain cache coherency. [[Scalable Coherent Interface]] (SCI) is an [[IEEE]] standard defining a directory-based cache coherency protocol to avoid scalability limitations found in earlier multiprocessor systems. For example, SCI is used as the basis for the NumaConnect technology.<ref>{{Cite web |title= The Scalable Coherent Interface and Related Standards Projects |author= David B. Gustavson |publisher= [[Stanford Linear Accelerator Center]] |date= September 1991 |work= SLAC Publication 5656 |url= http://www.slac.stanford.edu/cgi-wrap/getdoc/slac-pub-5656.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.slac.stanford.edu/cgi-wrap/getdoc/slac-pub-5656.pdf |archive-date=2022-10-09 |url-status=live |access-date= January 27, 2014 }}</ref><ref>{{cite web |url=http://www.numascale.com/numa_technology.html |title=The NumaChip enables cache coherent low cost shared memory |publisher=Numascale.com |access-date=2014-01-27 |archive-url=https://web.archive.org/web/20140122115025/http://www.numascale.com/numa_technology.html |archive-date=2014-01-22 |url-status=dead }}</ref>