Editing Motorola 88000 (section)

===Motorola's approach===
RISC designs were a conscious effort to tailor the processor to the types of operations being called by the [[compiler]]s on that platform, in the case of Unix workstations, the [[C programming language]]. The seminal [[IBM 801]] project had noted that compilers generally did not use the vast majority of the instructions available to them, and instead used the simplest version of the instructions, often because these performed the fastest. Yet the circuitry providing the other versions of these instructions added overhead even to the simplest version. Removing these unused instructions from the CPU eliminated this overhead and freed up significant room on the chip. This gave room to increase the number of [[processor register]]s, which had a far greater impact on performance than the removed special-case instructions. For this reason, the RISC concept can be said to be driven by the real-world design of compilers.{{sfn|Lid}}

Motorola's articles on the 88000 design speak of single-cycle instructions, large [[processor register]] files and other hallmarks of the RISC concept, but don't mention the word "RISC" even once.{{sfn|Alsup|1990}} As existing RISC designs had entered the market already, the company decided that it would not attempt to compete with these and would instead produce the world's most powerful processor. To do this, it took design notes from one of the fastest computers of a previous era, the [[CDC 6600]] [[supercomputer]]. In particular, it adopted the 6600's concept of a [[Scoreboarding|scoreboard]]. Scoreboarding allowed the CPU to examine the instruction's use of registers and immediately dispatch those that did not rely on previous calculations that were not yet complete; this allowed the instructions to be re-ordered to allow ones that had their required data to run while others had their data loaded from the cache or memory. This instruction reordering could improve usage by as much as 35%.{{sfn|Alsup|1990|p=51}}

The design also used separate data and instruction address buses. This was costly in terms of pin count; both the instruction and data caches had 32 pins for their address and 32 pins for the data, meaning the complete system used 128 pins on the "P-bus". This design was based on the observation that only about one-third of operations were memory-related; the rest were operating on data already read. This strongly favored having a dedicated instruction pathway to an external instruction cache. The caches and associated [[memory management unit]]s (MMU) were initially external, a cache controller could be connected to either the data or instruction buses, and up to four controllers could be used on either bus. Internally there were three 32-bit buses, connected to the internal units in different ways as required for reading and writing data to the registers.{{sfn|Alsup|1990|p=49}}

Another feature of the new design was its built-in support for specialized co-processors, or "special function units", or SFUs.{{sfn|Alsup|1990|p=49}} In addition to the internal commands supported out of the box, it set aside blocks of 256 instructions that could be used by co-processors. This was aimed at designers who wished to customize the system; new functional units could be added without affecting the existing [[instruction set architecture]], ensuring software compatibility for the main functionality.{{sfn|Lid}} Every 88000 came with SFU1 already installed, the [[floating point unit]] (FPU).{{sfn|Alsup|1990|p=49}} The branch and jump instructions incorporate a [[delay slot|delayed branch]] option (.n), which can be specified to ensure that the subsequent sequential instruction is executed before the branch target instruction, irrespective of the branch condition.<ref>{{Cite web |url=http://www.bitsavers.org/components/motorola/88000/MC88100_RISC_Microprocessor_Users_Manual_2ed_1990.pdf#page=81 |title=MC88100 RISC Microprocessor User's Manual |page=81(3-26) |accessdate=2023-12-21}}</ref> Placing branch instruction or other instruction which may change the instruction pointer, in the branch delay slot is deprecated to maintain future compatibility.<ref>{{Cite web |url=http://www.bitsavers.org/components/motorola/88000/MC88100_RISC_Microprocessor_Users_Manual_2ed_1990.pdf#page=88 |title=MC88100 RISC Microprocessor User's Manual |page=88(3-33) |accessdate=2023-12-30}}</ref>