Editing Motorola 68030 (section)

==Technical data==
{| class="wikitable"
| CPU [[clock rate]] || 16, 20, 25, 33, 40, 50&nbsp;MHz, except for MC68EC030 available in 25 and 40&nbsp;MHz ||<ref name=m30/>
|-
|             || Internal [[modified Harvard architecture#Split-cache (or almost-von-Neumann) architecture|split-cache modified Harvard architecture]]     ||<ref name=m30>{{cite web|url=http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MC68030|title=MC68030 Product Summary Page|date=2012|website=Freescale|archive-url=https://web.archive.org/web/20141006204732/http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MC68030|archive-date=October 6, 2014}}</ref>
|-
| Address bus || 32 bit ||<ref name=cw>{{cite web|url=http://www.cpu-world.com/CPUs/68030/index.html|website=cpu-world.com|title=Motorola 68030 (MC68030) microprocessor family|date=November 17, 2012}}</ref>
|-
| Data bus    || 32 bit ||<ref name=cw/>
|-
| Cache       || 256 bytes each for instruction and data, 16 lines of 4 entries of 4 bytes each, direct mapped ||<ref name=m30/><ref name="um"/>
|-
|             || dynamic bus sizing ||<ref name=m30/>
|-
|             || burst memory interface ||<ref name=m30/>
|-
| Performance || 18 MIPS @ 50&nbsp;MHz ||<ref name=m30/>
|}