Editing Motorola 68020 (section)

===020 concept emerges===
As this effort was ongoing, Motorola was canvassing their customers for their desires for future developments in the line. These all pointed to a fully 32-bit implementation. Those using the 68k in Unix systems also stated they would purchase a [[floating-point unit]] for every one of the machines if one was available.{{sfn|Oral|2007|p=22}}

The original 68000 had been designed as a hybrid 16/32-bit system largely because the maximum number of pins available on [[dual inline package]]s (DIPs) was 64, and even at that size, packaging of this size was highly problematic.{{sfn|Oral|2007|p=9}} By reducing the number of [[address bus|address pins]] to 24, and the [[data bus|data pins]] to only 16, there were enough free pins to implement all the other needed lines, like interrupts and power supplies. The 24-pin address bus meant that the memory could only be 16&nbsp;MB in total, which was at this point becoming a limitation. The 16-bit data bus meant reading a 32-bit word from that memory required two bus cycles.

A design that had 32 pins for both the address and data busses would access data twice as fast, making the machine that much faster even with no other changes. Moving to 32-bit addressing would also make the implementation of virtual memory easier, and allow for more than 16&nbsp;MB of [[random access memory]]. But doing so would also demand a much higher total pin count. By the early 1980s, similar limitations on all modern CPU designs led to the introduction of the [[pin grid array]] that replaced the DIP. For the new project, Motorola selected a 169-pin layout, giving them plenty of room to work with. The design ultimately used only 114 of them.

A great debate broke out about how to refer to the underlying design of the new chip in marketing materials. Technically, the 020 was moving from the long-established [[NMOS logic]] design to a [[CMOS]] layout, which requires two transistors per gate. Common knowledge of the era suggested that CMOS cost four times as much as NMOS, and there was a significant amount of the market that believed "CMOS equals bad."{{sfn|Oral|2007|p=29}}