Editing Kendall Square Research (section)

=== Hardware ===
The KSR-1 processor was implemented as a four-chip set in 1.2 micrometer complementary metal–oxide–semiconductor ([[CMOS]]). These chips were: the cell execution unit, the [[floating point unit]], the [[arithmetic logic unit]], and the external I/O unit (XIO). The CEU handled instruction fetch (two per clock), and all operations involving memory, such as loads and stores. 40-bit addresses were used, going to full 64-bit addresses later. The integer unit had 32, 64-bit-wide registers. The [[floating point]] unit is discussed below. The XIO had the capacity of 30 [[megabyte|MB]]/s throughput to I/O devices. It included 64 control and data registers.

The KSR processor was a 2-wide VLIW, with instructions of 6 types: memory reference (load and store), execute, control flow, memory control, I/O, and inserted. Execute instructions included arithmetic, logical, and type conversion. They were usually triadic [[processor register|register]] in format. Control flow refers to branches and jumps. Branch [[instruction set|instructions]] were two cycles. The programmer (or compiler) could implicitly control the ''quashing'' behavior of the subsequent two instructions that would be initiated during the branch. The choices were: always retain the results, retain results if branch test is true, or retain results if branch test is false. Memory control provided synchronization primitives. I/O instructions were provided. Inserted instructions were forced into a flow by a [[coprocessor]]. Inserted load and store were used for [[direct memory access]] (DMA) transfers. Inserted memory instructions were used to maintain cache coherency. New coprocessors could be interfaced with the inserted instruction mechanism. [[IEEE 754|IEEE standard floating point]] arithmetic was supported. Sixty-four 64-bit wide registers were included.

The following example of KSR assembly performs an indirect procedure call to an address held in the procedure's constant block, saving the return address in register <code>c14</code>.  It also saves the frame pointer, loads integer register zero with the value 3, and increments integer register 31 without changing the condition codes.  Most instructions have a [[delay slot]] of 2 cycles and the delay slots are not [[interlock]]ed, so must be scheduled explicitly, else the resulting [[hazard]] means wrong values are sometimes loaded.

<pre>
finop			; movb8_8 %i2,%c10
finop			; cxnop
finop			; cxnop
add8.ntr 75,%i31,%i31	; ld8 8(%c10),%c4
finop			; st8 %fp,504(%sp)
finop                   ; cxnop
movi8 3, %i0            ; jsr %c14,16(%c4)
</pre>

In the KSR design, all of the memory was treated as cache.  The design called for no ''home'' location- to reduce storage overheads and to software transparently, dynamically migrate/replicate memory based on where it was utilized;   a [[Harvard architecture]], separate [[bus (computing)|bus]] for instructions and memory was used. Each node board contained 256 [[kilobyte|KB]] of I-cache and D-cache, essentially primary cache. At each node was 32 MB of memory for main cache. The system level architecture was shared virtual memory, which was physically distributed in the machine. The programmer or application only saw one contiguous address space, which was spanned by a 40-bit address. Traffic between nodes traveled at up to 4 gigabytes per second. The 32 megabytes per node, in aggregate, formed the physical memory of the machine.

Specialized [[input/output]] processors could be used in the system, providing scalable I/O. A 1088 node KSR1 could have 510 I/O channels with an aggregate in excess of 15 [[gigabyte|GB]]/s. Interfaces such as [[Ethernet]], [[FDDI]], and [[HIPPI]] were supported.