Editing Intel i860 (section)

==Performance==
On paper, performance was impressive for a single-chip solution; however, real-world performance was anything but. One problem, perhaps unrecognized at the time, was that runtime code paths are difficult to predict, meaning that it becomes exceedingly difficult to order instructions properly at [[compile time]]. For instance, an instruction to add two numbers will take considerably longer if those numbers are not in the cache, yet there is no way for the programmer to know if they are or not. If an incorrect guess is made, the entire pipeline will stall, waiting for the data. The entire i860 design was premised on the compiler writing instructions that executed this task efficiently, which proved almost impossible in practice. While theoretically capable of peaking at about 60-80 MFLOPS for both [[single precision]] and [[double precision]] for the XP versions,<ref>{{cite web | title = Intel i860 : 64-Bit Microprocessor | url = http://www.microprocessor.sscc.ru/i860.html | archive-url   = https://web.archive.org/web/20090623025958/http://www.microprocessor.sscc.ru/i860.html | archive-date  = 2009-06-23 | access-date = 2013-09-27 | author = Oleg Yu. Repin, Alexei S. Pylkin | year = 2000 | publisher = sscc.ru, ICMMG }}</ref> manually written [[Assembly language#Assembler|assembler code]] managed to get up to only about 40 MFLOPS, and most compilers had difficulty getting even 10 MFLOPs.<ref>{{cite report
 | first1 = D.H.
 | last1 = Bailey
 | first2 = E.
 | last2 = Barszcz
 | first3 = R.A.
 | last3 = Fatoohi
 | first4 = H.D.
 | last4 = Simon
 | first5 = S.
 | last5 = Weeratunga
 | title = Performance Results on the Intel Touchstone Gamma Prototype
 | publisher = NASA Ames Research Center
 | date = 1990
 | url = https://www.nas.nasa.gov/assets/pdf/techreports/1990/rnr-90-007.pdf
 | access-date = 2016-07-10
 | archive-date = 2016-12-21
 | archive-url = https://web.archive.org/web/20161221195710/https://www.nas.nasa.gov/assets/pdf/techreports/1990/rnr-90-007.pdf
 | url-status = dead
 }}</ref> The later [[IA-64|Itanium]] architecture, also a VLIW design, suffered again from the problem of compilers incapable of delivering sufficiently optimized code.

Another serious problem was the lack of any solution to handle [[context switch]]ing quickly. The i860 had several pipelines (for the ALU and FPU parts) and an interrupt could spill them and require them all to be re-loaded. This took 62 cycles in the best case, and almost 2000 cycles in the worst. The latter is 1/20000th of a second at 40&nbsp;MHz (50 microseconds), an eternity for a CPU. This largely eliminated the i860 as a general purpose CPU.