Editing Intel 8088 (section)

===Performance===
Depending on the [[clock frequency]], the number of memory [[wait state]]s, as well as on the characteristics of the particular application program, the ''average'' performance for the Intel 8088 ranged approximately from 0.33 to 1&nbsp;million [[instructions per second]].<ref>{{cite web|url=http://www.olympusmicro.com/micd/galleries/chips/intel8088a.html|title=Olympus MIC-D: Integrated Circuit Gallery - Intel 8088 Microprocessor|archive-url=https://web.archive.org/web/20090519154800/http://www.olympusmicro.com/micd/galleries/chips/intel8088a.html|archive-date=May 19, 2009|url-status=dead}}</ref> Meanwhile, the <code>mov ''reg,reg''</code> and <code>[[Arithmetic logic unit|ALU]]{{efn|ALU stands for one of the instructions ADD, ADC, SUB, SBC, CMP, AND, OR, XOR, TEST.}} ''reg,reg''</code> instructions, taking two and three cycles respectively, yielded an ''absolute peak'' performance of between {{frac|1|3}} and {{frac|1|2}}&nbsp;MIPS per MHz, that is, somewhere in the range 3–5&nbsp;MIPS at 10&nbsp;MHz.

The speed of the execution unit (EU) and the bus of the 8086 CPU was well balanced; with a typical instruction mix, an 8086 could execute instructions out of the prefetch queue a good bit of the time.  Cutting down the bus to eight bits made it a serious bottleneck in the 8088.  With the speed of instruction fetch reduced by 50% in the 8088 as compared to the 8086, a sequence of fast instructions can quickly drain the four-byte prefetch queue.  When the queue is empty, instructions take as long to complete as they take to fetch.  Both the 8086 and 8088 take four clock cycles to complete a bus cycle; whereas for the 8086 this means four clocks to transfer two bytes, on the 8088 it is four clocks per byte.  Therefore, for example, a two-byte shift or rotate instruction, which takes the EU only two clock cycles to execute, actually takes eight clock cycles to complete if it is not in the prefetch queue.  A sequence of such fast instructions prevents the queue from being filled as fast as it is drained, and 
in general, because so many basic instructions execute in fewer than four clocks per instruction byte&mdash;including almost all the ALU and data-movement instructions on register operands and some of these on memory operands&mdash;it is practically impossible to avoid idling the EU in the 8088 at least {{frac|1|4}} of the time while executing useful real-world programs, and it is not hard to idle it half the time.  In short, an 8088 typically runs about half as fast as 8086 clocked at the same rate, because of the bus bottleneck (the only major difference).

A side effect of the 8088 design, with the slow bus and the small prefetch queue, is that the speed of code execution can be very dependent on instruction order.  When programming the 8088, for CPU efficiency, it is vital to interleave long-running instructions with short ones whenever possible.  For example, a repeated string operation or a shift by three or more will take long enough to allow time for the 4-byte prefetch queue to completely fill.  If short instructions (i.e. ones totaling few bytes) are placed between slower instructions like these, the short ones can execute at full speed out of the queue.  If, on the other hand, the slow instructions are executed sequentially, back to back, then after the first of them the bus unit will be forced to idle because the queue will already be full, with the consequence that later more of the faster instructions will suffer fetch delays that might have been avoidable.  As some instructions, such as single-bit-position shifts and rotates, take literally 4 times as long to fetch as to execute,{{efn|On the 8088, a shift instruction with an implied shift count of 1, which can execute in two clock cycles, is two bytes long and so takes eight clock cycles to fetch.}} the overall effect can be a slowdown by a factor of two or more.  If those code segments are the bodies of loops, the difference in execution time may be very noticeable on the human timescale.

The 8088 is also (like the 8086) slow at accessing memory.  The same ALU that is used to execute arithmetic and logic instructions is also used to calculate effective addresses.  There is a separate adder for adding a shifted segment register to the offset address, but the offset EA itself is always calculated entirely in the main ALU.  Furthermore, the loose coupling of the EU and BIU (bus unit) inserts communication overhead between the units, and the four-clock period bus transfer cycle is not particularly streamlined.  Contrast this with the two-clock period bus cycle of the 6502 CPU and the 80286's three-clock period bus cycle with pipelining down to two cycles for most transfers.  Most 8088 instructions that can operate on either registers or memory, including common ALU and data-movement operations, are at least four times slower for memory operands than for only register operands.  Therefore, efficient 8088 (and 8086) programs avoid repeated access of memory operands when possible, loading operands from memory into registers to work with them there and storing back only the finished results.  The relatively large general register set of the 8088 compared to its contemporaries assists this strategy.  When there are not enough registers for all variables that are needed at once, saving registers by pushing them onto the stack and popping them back to restore them is the fastest way to use memory to augment the registers, as the stack PUSH and POP instructions are the fastest memory operations.  The same is probably not true on the 80186 and later; they have dedicated address ALUs and perform memory accesses much faster than the 8088 and 8086.

Finally, because calls, jumps, and interrupts reset the prefetch queue, and because loading the IP register requires communication between the EU and the BIU (since the IP register is in the BIU, not in the EU, where the general registers are), these operations are costly.  All jumps and calls take at least 15 clock cycles.  Any conditional jump requires four clock cycles if not taken, but if taken, it requires 16 cycles in addition to resetting the prefetch queue; therefore, conditional jumps should be arranged to be not taken most of the time, especially inside loops.  In some cases, a sequence of logic and movement operations is faster than a conditional jump that skips over one or two instructions to achieve the same result.

Intel datasheets for the 8086 and 8088 advertised the dedicated multiply and divide instructions (MUL, IMUL, DIV, and IDIV), but they are very slow, on the order of 100–200 clock cycles each.  Many simple multiplications by small constants (besides powers of 2, for which shifts can be used) can be done much faster using dedicated short subroutines.  The 80286 and 80386 each greatly increase the execution speed of these multiply and divide instructions.{{efn|Most of the technical information in this section is sourced from the Intel iAPX 86,88 User's Manual, August 1981 (Order Number: 210201-001) by Intel Corporation.}}