Editing Intel 8080 (section)

===Programming model===
[[File:Intel 8080 arch.svg|right|thumb|i8080 microarchitecture]]
{| class="infobox" style="font-size:88%;width:34em;"
|+ Intel 8080 registers
|-
| style="text-align:center;"| <sup>1</sup><sub>5</sub>
| style="text-align:center;"| <sup>1</sup><sub>4</sub>
| style="text-align:center;"| <sup>1</sup><sub>3</sub>
| style="text-align:center;"| <sup>1</sup><sub>2</sub>
| style="text-align:center;"| <sup>1</sup><sub>1</sub>
| style="text-align:center;"| <sup>1</sup><sub>0</sub>
| style="text-align:center;"| <sup>0</sup><sub>9</sub>
| style="text-align:center;"| <sup>0</sup><sub>8</sub>
| style="text-align:center;"| <sup>0</sup><sub>7</sub>
| style="text-align:center;"| <sup>0</sup><sub>6</sub>
| style="text-align:center;"| <sup>0</sup><sub>5</sub>
| style="text-align:center;"| <sup>0</sup><sub>4</sub>
| style="text-align:center;"| <sup>0</sup><sub>3</sub>
| style="text-align:center;"| <sup>0</sup><sub>2</sub>
| style="text-align:center;"| <sup>0</sup><sub>1</sub>
| style="text-align:center;"| <sup>0</sup><sub>0</sub>
| ''(bit position)''
|- 16
|colspan="17" | '''Main registers''' <br/>
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| A
| style="text-align:center;background:#DDD" colspan="8"| Flags
| style="width:auto; background:white; color:black;"| '''P'''rogram '''S'''tatus '''W'''ord
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| B
| style="text-align:center;" colspan="8"| C
| style="background:white; color:black;"| '''B'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| D
| style="text-align:center;" colspan="8"| E
| style="background:white; color:black;"| '''D'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| H
| style="text-align:center;" colspan="8"| L
| style="background:white; color:black;"| '''H''' (indirect address)
|- 
|colspan="17" | '''Index registers''' <br/>
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| SP
| style="background:white; color:black;"| '''S'''tack '''P'''ointer
|- 
|colspan="17" | '''Program counter''' <br/>
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| PC
| style="background:white; color:black;"| '''P'''rogram '''C'''ounter
|- 
|colspan="17" | '''Status register'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="8" | &nbsp;
| style="text-align:center;"| [[Sign flag|S]]
| style="text-align:center;"| [[Zero flag|Z]]
| style="text-align:center;"| 0
| style="text-align:center;"| [[Half-carry flag|<sup>A</sup><sub>C</sub>]]
| style="text-align:center;"| 0
| style="text-align:center;"| [[Parity flag|P]]
| style="text-align:center;"| 1
| style="text-align:center;"| [[Carry flag|C]]
| style="background:white; color:black" | Flags <ref name="AssyLang">{{cite book |title=8080 Assembly Language Programming Manual |date=1975 |publisher=Intel |page=22 |edition=Rev B |url=https://archive.org/download/intel-8080-assembly-language-programming-manual-1975/Intel%208080%20Assembly%20Language%20Programming%20Manual%20%281975%29.pdf |access-date=29 February 2024}}</ref>
|}

The Intel 8080 is the successor to the [[Intel 8008|8008]]. It uses the same basic [[instruction set]] and [[Processor register|register]] model as the 8008, although it is neither [[Source-code compatibility|source code compatible]] nor [[Binary-code compatibility|binary code compatible]] with its predecessor. Every instruction in the 8008 has an equivalent instruction in the 8080. The 8080 also adds 16-bit operations in its instruction set. Whereas the 8008 required the use of the HL register pair to indirectly access its 14-bit memory space, the 8080 added addressing modes to allow direct access to its full 16-bit memory space. The internal 7-level push-down [[call stack]] of the 8008 was replaced by a dedicated 16-bit stack-pointer (SP) register. The 8080's 40-pin [[Dual in-line package|DIP packaging]] permits it to provide a 16-bit [[address bus]] and an 8-bit [[Bus (computing)|data bus]], enabling access to 64&nbsp;[[Kibibyte|KiB]] (2<sup>16</sup> bytes) of memory.

====Registers====
The processor has seven 8-bit [[processor register|registers]] (A, B, C, D, E, H, and L), where A is the primary 8-bit accumulator. The other six registers can be used as either individual 8-bit registers or in three 16-bit register pairs (BC, DE, and HL, referred to as B, D and H in Intel documents) depending on the particular instruction. Some instructions also enable the HL register pair to be used as a (limited) 16-bit accumulator. A pseudo-register M, which refers to the dereferenced memory location pointed to by HL, can be used almost anywhere other registers can be used. The 8080 has a 16-bit [[Stack-based memory allocation|stack pointer]] to memory, replacing the 8008's internal [[stack (data structure)|stack]], and a 16-bit [[program counter]].

====Flags====
The processor maintains internal [[flag word|flag bits]] (a [[status register]]), which indicate the results of arithmetic and logical instructions. Only certain instructions affect the flags. The flags are:
* [[Sign flag|Sign]] (S), set if the result is negative.
* [[Zero flag|Zero]] (Z), set if the result is zero.
* [[Parity flag|Parity]] (P), set if the number of 1 bits in the result is even.
* [[Carry flag|Carry]] (C), set if the last addition operation resulted in a carry or if the last subtraction operation required a borrow.
* [[Half-carry flag|Auxiliary carry]] (AC or H), used for [[binary-coded decimal]] arithmetic (BCD).

The carry bit can be set or complemented by specific instructions. Conditional-branch instructions test the various flag status bits. The accumulator and the flags together are called the PSW, or program status word. PSW can be pushed to or popped from the stack.

====Commands, instructions====
As with many other 8-bit processors, all instructions are encoded in one byte (including register numbers, but excluding immediate data), for simplicity. Some can be followed by one or two bytes of data, which can be an immediate operand, a memory address, or a port number. Like more advanced processors, it has automatic CALL and RET instructions for multi-level procedure calls and returns (which can even be conditionally executed, like jumps) and instructions to save and restore any 16-bit register pair on the machine stack. Eight one-byte call instructions ({{code|RST}}) for subroutines exist at the fixed addresses 00h, 08h, 10h, ..., 38h. These are intended to be supplied by external hardware in order to invoke a corresponding [[interrupt service routine]], but are also often employed as fast [[system call]]s. The instruction that executes slowest is {{code|XTHL}}, which is used for exchanging the register pair HL with the value stored at the address indicated by the stack pointer.

=====8-bit instructions=====
All 8-bit operations with two operands can only be performed on the 8-bit [[Accumulator (computing)|accumulator]] (the A register). The other operand can be either an immediate value, another 8-bit register, or a memory byte addressed by the 16-bit register pair HL. Increments and decrements can be performed on any 8 bit register or an HL-addressed memory byte. Direct copying is supported between any two 8-bit registers and between any 8-bit register and an HL-addressed memory byte. Due to the regular encoding of the {{code|MOV}} instruction (using a quarter of available opcode space), there are redundant codes to copy a register into itself ({{code|MOV B,B}}, for instance), which are of little use, except for delays. However, the systematic opcode for {{code|MOV M,M}} is instead used to encode the halt ([[HLT (x86 instruction)|{{code|HLT}}]]) instruction, halting execution until an external reset or interrupt occurs.

=====16-bit operations=====
Although the 8080 is generally an 8-bit processor, it has limited abilities to perform 16-bit operations. Any of the three 16-bit register pairs (BC, DE, or HL, referred to as B, D, H in Intel documents) or SP can be loaded with an immediate 16-bit value (using {{code|LXI}}), incremented or decremented (using {{code|INX}} and {{code|DCX}}), or added to HL (using {{code|DAD}}). By adding HL to itself, it is possible to achieve the same result as a 16-bit arithmetical left shift with one instruction. The only 16-bit instructions that affect any flag is {{code|DAD}}, which sets the CY (carry) flag in order to allow for programmed 24-bit or 32-bit [[arithmetic]] (or larger), needed to implement [[floating-point arithmetic]]. BC, DE, HL, or PSW can be copied to and from the stack using {{code|PUSH}} and {{code|POP}}. A stack frame can be allocated using {{code|DAD SP}} and {{code|SPHL}}. A branch to a computed pointer can be executed with {{code|PCHL}}. {{code|LHLD}} loads HL from directly addressed memory and {{code|SHLD}} stores HL likewise. The {{code|XCHG}}<ref>[http://www.classiccmp.org/dunfield/r/8080.txt 8080 instruction encoding] {{Webarchive|url=https://web.archive.org/web/20180305170555/http://www.classiccmp.org/dunfield/r/8080.txt |date=March 5, 2018 }}. ClassicCMP.org. Retrieved on October 23, 2011.</ref> instruction exchanges the values of the HL and DE register pairs. {{code|XTHL}}exchanges last item pushed on stack with HL.

=====Instruction set=====
{|class="wikitable" style="text-align:center"
!colspan=8| Opcode ||colspan=2| Operands ||rowspan=2| Mnemonic || rowspan=2| Clocks ||rowspan=2| Description
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| NOP || 4 ||align=left| No operation
|-
| 0 || 0 ||colspan=2|RP || 0 || 0 || 0 || 1 || ''datlo'' || ''dathi'' ||align=left| LXI ''rp,data'' || 10 ||align=left| RP ← ''data''
|-
| 0 || 0 ||colspan=2|RP || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| STAX ''rp'' || 7 ||align=left| (RP) ← A [BC or DE only]
|-
| 0 || 0 ||colspan=2|RP || 0 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| INX ''rp'' || 5 ||align=left| RP ← RP + 1
|-
| 0 || 0 ||colspan=3|DDD || 1 || 0 || 0 || &mdash; || &mdash; ||align=left| INR ''ddd'' || 5/10 ||align=left| DDD ← DDD + 1
|-
| 0 || 0 ||colspan=3|DDD || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| DCR ''ddd'' || 5/10 ||align=left| DDD ← DDD - 1
|-
| 0 || 0 ||colspan=3|DDD || 1 || 1 || 0 || ''data'' || &mdash; ||align=left| MVI ''ddd,data'' || 7/10 ||align=left| DDD ← data
|-
| 0 || 0 ||colspan=2|RP || 1 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| DAD ''rp'' || 10 ||align=left| HL ← HL + RP
|-
| 0 || 0 ||colspan=2|RP || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| LDAX ''rp'' || 7 ||align=left| A ← (RP) [BC or DE only]
|-
| 0 || 0 ||colspan=2|RP || 1 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| DCX ''rp'' || 5 ||align=left| RP ← RP - 1
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| RLC || 4 ||align=left| A<sub>1-7</sub> ← A<sub>0-6</sub>; A<sub>0</sub> ← Cy ← A<sub>7</sub>
|-
| 0 || 0 || 0 || 0 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| RRC || 4 ||align=left| A<sub>0-6</sub> ← A<sub>1-7</sub>; A<sub>7</sub> ← Cy ← A<sub>0</sub>
|-
| 0 || 0 || 0 || 1 || 0 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| RAL || 4 ||align=left| A<sub>1-7</sub> ← A<sub>0-6</sub>; Cy ← A<sub>7</sub>; A<sub>0</sub> ← Cy
|-
| 0 || 0 || 0 || 1 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| RAR || 4 ||align=left| A<sub>0-6</sub> ← A<sub>1-7</sub>; Cy ← A<sub>0</sub>; A<sub>7</sub> ← Cy
|-
| 0 || 0 || 1 || 0 || 0 || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| SHLD ''add'' || 16 ||align=left| (add) ← HL
|-
| 0 || 0 || 1 || 0 || 0 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| DAA || 4 ||align=left| If A<sub>0-3</sub> > 9 OR AC = 1 then A ← A + 6;
then if A<sub>4-7</sub> > 9 OR Cy = 1 then A ← A + 0x60
|-
| 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| LHLD ''add'' || 16 ||align=left| HL ← (add)
|-
| 0 || 0 || 1 || 0 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| CMA || 4 ||align=left| A ← ¬A
|-
| 0 || 0 || 1 || 1 || 0 || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| STA ''add'' || 13 ||align=left| (add) ← A
|-
| 0 || 0 || 1 || 1 || 0 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| STC || 4 ||align=left| Cy ← 1
|-
| 0 || 0 || 1 || 1 || 1 || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| LDA ''add'' || 13 ||align=left| A ← (add)
|-
| 0 || 0 || 1 || 1 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| CMC || 4 ||align=left| Cy ← ¬Cy
|-
| 0 || 1 ||colspan=3|DDD ||colspan=3|SSS || &mdash; || &mdash; ||align=left| MOV ''ddd,sss'' ||5/7 ||align=left| DDD ← SSS
|-
| 0 || 1 || 1 || 1 || 0 || 1|| 1 || 0 || &mdash; || &mdash; ||align=left| HLT || 7 ||align=left| Halt
|-
| 1 || 0 ||colspan=3|ALU ||colspan=3|SSS || &mdash; || &mdash; ||align=left| ADD ADC SUB SBB ANA XRA ORA CMP ''sss'' || 4/7 ||align=left| A ← A [ALU operation] SSS
|-
| 1 || 1 ||colspan=3|CC || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| Rcc (RET conditional) || 5/11 ||align=left| If cc true, PC ← (SP), SP ← SP + 2
|-
| 1 || 1 ||colspan=2|RP || 0 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| POP ''rp'' || 10 ||align=left| RP ← (SP), SP ← SP + 2
|-
| 1 || 1 ||colspan=3|CC || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| Jcc ''add'' (JMP conditional) || 10 ||align=left| If cc true, PC ← add
|-
| 1 || 1 || 0 || 0 || 0 || 0 || 1 || 1 || ''addlo'' || ''addhi'' ||align=left| JMP ''add'' || 10 ||align=left| PC ← add
|-
| 1 || 1 ||colspan=3|CC || 1 || 0 || 0 || ''addlo'' || ''addhi'' ||align=left| Ccc ''add'' (CALL conditional) || 11/17 ||align=left| If cc true, SP ← SP - 2, (SP) ← PC, PC ← add
|-
| 1 || 1 ||colspan=2|RP || 0 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| PUSH ''rp'' || 11 ||align=left| SP ← SP - 2, (SP) ← RP
|-
| 1 || 1 ||colspan=3|ALU || 1 || 1 || 0 || ''data'' || &mdash; ||align=left| ADI ACI SUI SBI ANI XRI ORI CPI ''data'' || 7 ||align=left| A ← A [ALU operation] data
|-
| 1 || 1 ||colspan=3|N || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| RST ''n'' || 11 ||align=left| SP ← SP - 2, (SP) ← PC, PC ← N x 8
|-
| 1 || 1 || 0 || 0 || 1 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| RET || 10 ||align=left| PC ← (SP), SP ← SP + 2
|-
| 1 || 1 || 0 || 0 || 1 || 1 || 0 || 1 || ''addlo'' || ''addhi'' ||align=left| CALL ''add'' || 17 ||align=left| SP ← SP - 2, (SP) ← PC, PC ← add
|-
| 1 || 1 || 0 || 1 || 0 || 0 || 1 || 1 || ''port'' || &mdash; ||align=left| OUT ''port'' || 10 ||align=left| Port ← A
|-
| 1 || 1 || 0 || 1 || 1 || 0 || 1 || 1 || ''port'' || &mdash; ||align=left| IN ''port'' || 10 ||align=left| A ← Port
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| XTHL || 18 ||align=left| HL ↔ (SP)
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| PCHL || 5 ||align=left| PC ← HL
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| XCHG || 4 ||align=left| HL ↔ DE
|-
| 1 || 1 || 1 || 1|| 0 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| DI || 4 ||align=left| Disable interrupts
|-
| 1 || 1 || 1 || 1 || 1 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| SPHL || 5 ||align=left| SP ← HL
|-
| 1 || 1 || 1 || 1 || 1 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| EI || 4 ||align=left| Enable interrupts
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || Clocks || Description
|-
!colspan=13|
|-
!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU||RP||
|-
|colspan=5| B || 0 || 0 || 0 ||colspan=2|NZ ||align=left|ADD ADI (A ← A + arg)|| BC
|-
|colspan=5| C || 0 || 0 || 1||colspan=2|Z||align=left|ADC ACI (A ← A + arg + Cy)|| DE
|-
|colspan=5| D || 0 || 1 || 0||colspan=2|NC ||align=left|SUB SUI (A ← A - arg)|| HL
|-
|colspan=5| E || 0 || 1 || 1||colspan=2|C ||align=left|SBB SBI (A ← A - arg - Cy)|| SP or PSW
|-
|colspan=5| H || 1 || 0 || 0||colspan=2|PO ||align=left|ANA ANI (A ← A ∧ arg)
|-
|colspan=5| L || 1 || 0 || 1||colspan=2|PE ||align=left|XRA XRI (A ← A ⊻ arg)
|-
|colspan=5| M || 1 || 1 || 0||colspan=2|P ||align=left|ORA ORI (A ← A ∨ arg)
|-
|colspan=5| A || 1 || 1 || 1||colspan=2|N||align=left|CMP CPI (A - arg)
|-
!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU||colspan=2|
|}