Editing Intel 4040 (section)

===4040===
[[Image:Intel_4040_arch.svg|right|thumb|i4040 microarchitecture. Note: the "data bus" is also used for addressing.]]
[[File:Intel 4040 processor pinout.png|thumb|Intel 4040 DIP chip [[pinout]]]]
The 4040 was essentially an expansion of the 4004, with additional pins, more registers and new instructions to take advantage of both.

The 4004 had a single ROM pin, whereas the 4040 added another ROM pin to allow two banks of ROM. This effectively increased the ROM address from 12 to 13 bits, or 8&nbsp;kB. Unlike later designs where the two lines could be [[Binary number|binary]] encoded and thus support four banks, the ROM chips used with the 4004 and 4040 used these lines like [[chip select]] pins, and thus the two lines could only support two banks.

The 4004 lacked [[interrupt]]s, a serious limitation.{{clarification needed|date=March 2025}} The 4040 added a new input pin for calling an interrupt, as well an output pin to indicate the interrupt signal had been noticed and was being acted on. As interrupts also need to save a return address, the stack register file was expanded to seven entries, up from three.<ref group=Note>by default only one level of interrupt was supported, as further servicing was disabled once an initial interrupt was acknowledged and could only re-enabled on RTI, essentially allowing three levels of subroutine stacking within an interrupt itself occurring within a three-deep subroutine, but detection could be forced back on with a specific command.</ref>

[[Interrupt handler]] code normally starts by saving out values in the registers to allow the interrupt code to use them, and then at the end it copies the values back from memory so that the processor returns to its original pre-interrupt state. With the multi-cycle memory access of the design, this would have been extremely slow. To address this, eight additional registers were added in a new "bank 1", the original sixteen registers retroactively becoming "bank 0". The idea was that programmers would attempt to place their critical data in the first eight registers of bank 0. When an interrupt was received, the handler code would call an instruction to swap banks, which would cause bank 1's registers to override bank 0's registers 0 through 7. The handler code would then use these eight registers for any local data, leaving the original values untouched. When the handler completed, it simply swapped bank 0 back in. This reduced the switching time to a single instruction, greatly improving interrupt response times.

Another addition was the input stop pin, and the associated output stop acknowledge. These could be used to stop the processor while the system performed [[input/output]] or other non-CPU tasks, but was more widely used for [[debugging]] by allowing the processor to be single-stepped. When the processor was in stopped mode, most of the chip hardware put into a low-drain, high-impedance condition, reducing power use. The machine cycle clocks were kept running for the benefit of external devices, including any interrupt controllers needed to wake the chip back up, which relied on these controllers staying in sync.

To take advantage of these new features, and to support the new logical <code>AND</code> and <code>OR</code> operators, the instruction set added 14 new instructions, bringing the total to 60.

{| class="infobox" style="font-size:88%;width:25em;"
|-
|+ Intel 4040 registers
|-
|
{| style="font-size:88%;"
|- 
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto;" | ''(bit position)''
|-
|colspan="14" | '''Accumulator'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="5"| 
| style="text-align:center; background:white" colspan="4"| 
| style="text-align:center;" colspan="4"| A
| style="width:auto; background:white; color:black;"| '''A'''ccumulator
|-
|colspan="14" | '''Index registers'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="5"| 
| style="text-align:center;" colspan="4"| R0
| style="text-align:center;" colspan="4"| R1
| style="width:auto; background:white; color:black;"| Index bank 0
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="5"| 
| style="text-align:center;" colspan="4"| R2
| style="text-align:center;" colspan="4"| R3
| style="width:auto; background:white; color:black;"| 
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="5"| 
| style="text-align:center;" colspan="4"| R4
| style="text-align:center;" colspan="4"| R5
| style="width:auto; background:white; color:black;"| 
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="5"| 
| style="text-align:center;" colspan="4"| R6
| style="text-align:center;" colspan="4"| R7
| style="width:auto; background:white; color:black;"| 
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="5"| 
| style="text-align:center;" colspan="4"| R8
| style="text-align:center;" colspan="4"| R9
| style="width:auto; background:white; color:black;"| 
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="5"| 
| style="text-align:center;" colspan="4"| R10
| style="text-align:center;" colspan="4"| R11
| style="width:auto; background:white; color:black;"| 
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="5"| 
| style="text-align:center;" colspan="4"| R12
| style="text-align:center;" colspan="4"| R13
| style="width:auto; background:white; color:black;"| 
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="5"| 
| style="text-align:center;" colspan="4"| R14
| style="text-align:center;" colspan="4"| R15
| style="width:auto; background:white; color:black;"| 
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="5"| 
| style="text-align:center;" colspan="4"| R0
| style="text-align:center;" colspan="4"| R1
| style="width:auto; background:white; color:black;"| Index bank 1
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="5"| 
| style="text-align:center;" colspan="4"| R2
| style="text-align:center;" colspan="4"| R3
| style="width:auto; background:white; color:black;"| 
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="5"| 
| style="text-align:center;" colspan="4"| R4
| style="text-align:center;" colspan="4"| R5
| style="width:auto; background:white; color:black;"| 
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="5"| 
| style="text-align:center;" colspan="4"| R6
| style="text-align:center;" colspan="4"| R7
| style="width:auto; background:white; color:black;"| 
|-
|colspan="14" | '''Program counter'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="13"| PC
| style="background:white; color:black;"| '''P'''rogram '''C'''ounter
|-
|colspan="14" | '''Push-down address call stack'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="13"| PC1
| style="background:white; color:black;"| Call level 1
|- style="background:silver;color:black"
| style="text-align:center;" colspan="13"| PC2
| style="background:white; color:black;"| Call level 2
|- style="background:silver;color:black"
| style="text-align:center;" colspan="13"| PC3
| style="background:white; color:black;"| Call level 3
|- style="background:silver;color:black"
| style="text-align:center;" colspan="13"| PC4
| style="background:white; color:black;"| Call level 4
|- style="background:silver;color:black"
| style="text-align:center;" colspan="13"| PC5
| style="background:white; color:black;"| Call level 5
|- style="background:silver;color:black"
| style="text-align:center;" colspan="13"| PC6
| style="background:white; color:black;"| Call level 6
|- style="background:silver;color:black"
| style="text-align:center;" colspan="13"| PC7
| style="background:white; color:black;"| Call level 7
|-
|colspan="14" | '''Condition codes'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="12" | 
| style="text-align:center;"| C
| style="background:white; color:black" | [[Carry flag|'''C'''arry flag]]
|} 
|}