Editing I486 (section)

===Differences between i386 and i486===
* An 8 [[Kilobyte|KB]] on-chip (level 1) [[Static random access memory|SRAM]] [[CPU cache|cache]] stores the most recently used instructions and data (16&nbsp;KB and/or [[Cache (computing)#Operation|write-back]] on some later models). The [[i386]] had no internal cache but supported a slower off-chip cache (not officially a [[level 2 cache]] because i386 had no internal level 1 cache).
* An enhanced external bus protocol to enable cache coherency and a new burst mode for memory accesses to fill a cache line of 16 bytes within five bus cycles. The 386 needed eight bus cycles to transfer the same amount of data.
* Tightly coupled{{efn|name=fn1|The 386, 286, and even the 8086 all had overlapping fetch, decode, execution (calculation), and write back; however, '''tightly pipelined''' usually means that all stages perform their respective duties within the same length time slot. In contrast '''loosely pipelined''' implies that some kind of buffering is used to decouple the units and allow them to work more independently. Both the original 8086 and the x86-chips of today are "loosely pipelined" in this sense, while the i486 and the original Pentium worked in a "tightly pipelined" manner for typical instructions. This included most "[[Complex instruction set computing|CISC]]" type instructions as well as the simple load/store-free "[[RISC]]-like" ones, although the most complex also used some dedicated [[microcode]] control.}} [[Instruction pipeline|pipelining]] completes a simple instruction like ALU ''reg,reg'' or ALU ''reg,im'' every clock cycle (after a latency of several cycles). The i386 needed two clock cycles.
* Integrated [[floating point unit|FPU]] (disabled or absent in [[Intel 80486SX|SX models]]) with a dedicated [[local bus]]; together with faster algorithms on more extensive hardware than in the i387, this performed floating-point calculations faster than the [[i386]]/[[i387]] combination.
* Improved [[memory management unit|MMU]] performance.
* New instructions: XADD, BSWAP, CMPXCHG, INVD, WBINVD, INVLPG.

Just as in the i386, a flat 4&nbsp;GB memory model could be implemented. All "segment selector" registers could be set to a neutral value in [[protected mode]], or to zero in [[real mode]], and using only the 32-bit "offset registers" (x86-terminology for general CPU registers used as address registers) as a linear 32-bit virtual address bypassing the segmentation logic. Virtual addresses were then normally mapped onto physical addresses by the paging system except when it was disabled (''real'' mode had no ''virtual'' addresses). Just as with the i386, circumventing memory segmentation could substantially improve performance for some [[operating systems]] and applications.

On a typical PC [[motherboard]], either four matched 30-pin (8-bit) [[SIMM]]s or one 72-pin (32-bit) SIMM per bank were required to fit the i486's [[32-bit computing|32-bit]] [[bus (computing)|data bus]]. The [[address bus]] used 30-bits (A31..A2) complemented by four byte-select pins (instead of A0,A1) to allow for any 8/16/32-bit selection. This meant that the limit of directly addressable physical memory was 4&nbsp;[[gigabyte]]s as well (2<sup>30</sup> ''32-bit'' words = 2<sup>32</sup> ''8-bit'' words).