Editing Hardware description language (section)

===Comparison with control-flow languages===
It is certainly possible to represent hardware semantics using traditional programming languages such as [[C++]], which operate on [[control flow]] semantics as opposed to [[data flow]], although to function as such, programs must be augmented with extensive and unwieldy [[Class library#Object and class libraries|class libraries]]. Generally, however, software programming languages do not include any capability for explicitly expressing time, and thus cannot function as hardware description languages. Before the introduction of [[System Verilog]] in 2002, [[C++]] integration with a [[Logic simulation|logic simulator]] was one of the few ways to use [[object-oriented programming]] in hardware verification. System Verilog is the first major HDL to offer object orientation and garbage collection.

Using the proper subset of hardware description language, a program called a synthesizer, or [[Logic synthesis|logic synthesis tool]], can infer hardware logic operations from the language statements and produce an equivalent netlist of generic hardware primitives{{technical statement|date=April 2014}} to implement the specified behaviour.{{Citation needed|date=July 2010}} Synthesizers generally ignore the expression of any timing constructs in the text. Digital logic synthesizers, for example, generally use [[Clock signal|clock edges]] as the way to time the circuit, ignoring any timing constructs. The ability to have a synthesizable subset of the language does not itself make a hardware description language.