Editing GE 645 (section)

=== Processor Modes ===
The GE-645 has two modes of Instruction Execution (Master and Slave) inherited from the GE-635, however it also adds another dimension by having two modes of memory addressing (Absolute and Appending). When the process is executing in Absolute Mode addressing is limited to 2<sup>18</sup> words of memory and any instructions are executed in Master mode. In comparison Append Mode calculates the address using "Appending Words" with an address space of 2<sup>24</sup> words and with instruction execution occurring in either Master or Slave modes.<ref name="AH82-00" /> 
==== Slave Mode ====
By default this is normal mode that the processor should be executing in at any point in time. Nearly all instructions will run in this mode aside from a small set of privileged instructions which cannot execute in this mode. Execution of such instructions will trigger an illegal procedure fault, also the ability to inhibit interrupts (bit 28 of instruction word) is forbidden. Format of instruction addresses is via the Appending Process.
==== Master Mode ====
In this mode the processor can execute all instructions and is able to inhibit interrupts while doing so. Like in Slave mode the default form of address formation is via the Appending Process.
==== Absolute Mode ====
All instructions can be executed in this mode and full access is given to any privileged features of the hardware. Interrupts can be inhibited and instruction fetching is limited to a 2<sup>18</sup> (18-bit) absolute address thus restricting the processor to only been able to access the lower 256 KW of physical core memory. The processor will switch to this mode in the event of a fault or interrupt and will remain in it until it executes transfer instruction whose operand address has been obtained via the appending process.

==== Appending Mode ====
By default this is normal mode of Memory addressing, both Master and Slave modes normally operate in this mode. Indirect words and operands are accessed via Appending Mechanism via the process of placing a 1 in bit 29 of the executed instruction. Effective addresses are thus either added to a base address, or the offset is linked to the base address. 
 
{| class="wikitable"
!Functions
! colspan="3" |Mode
|-
|
|Slave
|Master
|Absolute
|-
|Privileged instructions
|No
|Yes
|Yes
|-
|Interrupt inhibit (bit 28 of instruction word)
|No
|Yes
|Yes
|-
|Address for Instruction fetch
|Appending
|Appending
|Absolute
|-
|Address for Operand fetch
|Appending
|Appending
|Controlled by Bit 29 of instruction word
|-
|Restriction of access to other segments or pages
|Some
|Some (less restrictive than slave)
|N/A
|}