Editing Data General Nova (section)

===Design===
Cancelation of the PDP-X prompted de Castro to consider leaving DEC to build a system on his own. He was not alone; in late 1967 a group of like-minded engineers formed to consider such a machine. The group included Pat Green, a divisional manager; Richard Sogge, another hardware engineer; and Henry Burkhardt III, a software engineer.<ref>{{cite web |url=http://www.cpushack.com/2014/11/21/when-a-minicomputer-becomes-a-micro-the-dgc-micronova-mn601-and-602/ |title=When a Minicomputer becomes a Micro: the DGC microNOVA mN601 and 602 |date=21 November 2014 |website=The CPU Shack Museum}}</ref> In contrast to the PDP-X, the new effort focused on a single machine that could be brought to market quickly, as de Castro felt the PDP-X concept was far too ambitious for a small [[startup company]].{{sfn|Hendrie|2002|p=43}}

Discussing it with the others at DEC, the initial concept led to an 8-bit machine which would be less costly to implement.{{sfn|Hendrie|2002|p=43-44}} The group began talking with Herbert Richman, a salesman for [[Fairchild Semiconductor]] who knew the others through his contacts with DEC. At the time, Fairchild was battling with [[Texas Instruments]] and [[Signetics]] in the rapidly growing [[transistor-transistor logic|TTL]] market and were introducing new [[semiconductor device fabrication|fabs]] that allowed more complex designs. Fairchild's latest 9300 series allowed up to 96 gates per chip, and they had used this to implement a number of 4-bit chips like binary counters and [[shift register]]s.<ref name="Gianluca G.">{{cite web |url=https://apollo181.wixsite.com/apollo181/about |title=History of ALU 74181 in commercial minicomputers |author=Gianluca G. |date=2017}}</ref>

Using these ICs reduced the total IC count needed to implement a complete [[arithmetic logic unit]] (ALU), the core mathematical component of a CPU, allowing the expansion from an 8-bit design to 16-bit. This did require the expansion of the CPU from a single {{convert|15|x|15|in|cm}} [[printed circuit board]] to two, but such a design would still be significantly cheaper to produce than the PDP-8/I while still being more powerful and ASCII-based. A third board held the [[input/output]] circuitry and a complete system typically included another board with 4&nbsp;kB of [[random-access memory]]. A complete four-card system fit in a single rackmount chassis.{{sfn|Hendrie|2002|p=48}}

The boards were designed so they could be connected together using a printed circuit [[backplane]], with minimal manual wiring, allowing all the boards to be built in an automated fashion. This greatly reduced costs over the PDP-8/I, which consisted of many smaller boards that had to be wired together at the backplane, which was itself connected together using [[wire wrap]]. The larger-board construction also made the Nova more reliable, which made it especially attractive for industrial or lab settings.{{sfn|Hendrie|2002|p=48}}

The new design used a simple [[load–store architecture]]{{sfn|Supnik|2004}} which would reemerge in the RISC designs in the 1980s. Because the complexity of a [[flip-flop (electronics)|flip-flop]] was being rapidly reduced as they were implemented in chips, the design offset the lack of [[addressing mode]]s of the load–store design by adding four general-purpose [[accumulator (computing)|accumulators]], instead of the single register that would be found in similar low-cost offerings like the PDP series.{{sfn|Supnik|2004}}