Editing DDR SDRAM (section)

=== Modules ===
To increase memory capacity and bandwidth, chips are combined on a module. For instance, the 64-bit data bus for DIMM requires eight 8-bit chips, addressed in parallel. Multiple chips with common address lines are called a [[memory rank]]. The term was introduced to avoid confusion with chip internal '''rows''' and '''banks'''. A memory module may bear more than one rank. The term '''sides''' would also be confusing because it incorrectly suggests the physical placement of chips on the module. All ranks are connected to the same memory bus (address + data). The [[chip select]] signal is used to issue commands to specific rank.

Adding modules to the single memory bus creates additional electrical load on its drivers. To mitigate the resulting bus signaling rate drop and overcome the [[Von Neumann architecture#Von Neumann bottleneck|memory bottleneck]], new [[chipsets]] employ the [[dual-channel|multi-channel]] architecture.

{|class="wikitable" style="text-align:center;"
|+ Comparison of DDR SDRAM standards

! colspan="3" scope="col" | Name
! colspan="2" scope="col" | [[Chip (computing)|Chip]]
! colspan="3" scope="col" | [[Bus (computing)|Bus]]
! colspan="2" scope="col" | [[Memory timings|Timings]]
! rowspan="2" scope="col" | [[Voltage]]<br>{{Small|([[Volt|V]])}}

|- style="line-height:133%"
! scope="col" | Standard
! scope="col" | Type
! scope="col" | Module
! scope="col" |[[Clock rate]]<br>{{Small|([[MHz]])}}
! scope="col" | Cycle time<br>{{Small|([[Nanosecond|ns]])}}<ref>Cycle time is the inverse of the I/O bus clock frequency; e.g., 1/(100&nbsp;MHz) = 10&nbsp;ns per clock cycle.</ref>
! scope="col" | Clock rate<br>{{Small|(MHz)}}
! scope="col" | [[Transfer (computing)|Transfer rate]]<br>{{Small|(MT/s)}}
! scope="col" | [[Bandwidth (computing)|Bandwidth]]<br><small>([[MB/s]])</small>
! scope="col" | CL-T{{Sub|RCD}}-<br>T{{Sub|RP}}
! scope="col" | [[CAS latency]]<br>{{Small|(ns)}}

|-
! colspan="2" scope="row" | DDR-200
| PC-1600
| 100
| 10
| 100 
| 200
| 1600
| 2-2-2
| 20
| rowspan="3" | 2.5±0.2

|-
! colspan="2" scope="row" | DDR-266
| PC-2100
| {{frac|133|1|3}}
| 7.5
| {{frac|133|1|3}}
| {{Fraction|266|2|3}}
| {{frac|2133|1|3}}
| 2.5-3-3
| 18.75
|-
! colspan="2" scope="row" | DDR-333
| PC-2700
| {{frac|166|2|3}}
| 6
| {{frac|166|2|3}}
| {{frac|333|1|3}}
| {{frac|2666|2|3}}
| 2.5-3-3
| 15

|-
! rowspan="3" scope="row" | DDR-400
! A
| rowspan="3" | PC-3200
| rowspan="3" | 200
| rowspan="3" | 5
| rowspan="3" | 200
| rowspan="3" | 400
| rowspan="3" | 3200
| 2.5-3-3
| 12.5
| rowspan="3" | 2.6±0.1

|-
! B
| 3-3-3
| 15
|-
! C
| 3-4-4
| 15
|}

'''Note:''' All items listed above are specified by [[JEDEC]] as JESD79F.<ref>{{cite web|url=http://www.jedec.org/standards-documents/docs/jesd-79f|title=DOUBLE DATA RATE (DDR) SDRAM STANDARD - JEDEC|website=www.jedec.org}}</ref> All RAM data rates in-between or above these listed specifications are not standardized by JEDEC – often they are simply manufacturer optimizations using tighter tolerances or overvolted chips. The package sizes in which DDR SDRAM is manufactured are also standardized by JEDEC.

There is no architectural difference between DDR SDRAM modules. Modules are instead designed to run at different clock frequencies: for example, a PC-1600 module is designed to run at {{nowrap|100 MHz}}, and a PC-2100 is designed to run at {{nowrap|133 MHz}}. A module's clock speed designates the data rate at which it is guaranteed to perform, hence it is guaranteed to run at lower (''[[underclocking]]'') and can possibly run at higher (''[[overclocking]]'') clock rates than those for which it was made.<ref>{{Cite web|url=http://www.crucial.com/support/memory_speeds.aspx|title=What is the difference between PC-2100 (DDR-266), PC-2700 (DDR-333), and PC-3200 (DDR-400)?|publisher=Micron Technology|access-date=2009-06-01|archive-url=https://web.archive.org/web/20131203004412/http://www.crucial.com/support/memory_speeds.aspx|archive-date=2013-12-03|url-status=dead}}</ref>

DDR SDRAM modules for desktop computers, [[DIMM|dual in-line memory modules (DIMMs)]], have 184 pins (as opposed to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for notebook computers, [[SO-DIMM]]s, have 200 pins, which is the same number of pins as DDR2 SO-DIMMs. These two specifications are notched very similarly and care must be taken during insertion if unsure of a correct match. Most DDR SDRAM operates at a voltage of 2.5&nbsp;V, compared to 3.3&nbsp;V for SDRAM. This can significantly reduce power consumption. Chips and modules with the DDR-400/PC-3200 standard have a nominal voltage of 2.6&nbsp;V.

JEDEC Standard No. 21–C defines three possible operating voltages for 184 pin DDR, as identified by the key notch position relative to its centreline. Page 4.5.10-7 defines 2.5V (left), 1.8V (centre), TBD (right), while page 4.20.5–40 nominates 3.3V for the right notch position. The orientation of the module for determining the key notch position is with 52 contact positions to the left and 40 contact positions to the right.

Increasing the operating voltage slightly can increase maximum speed but at the cost of higher power dissipation and heating, and at the risk of malfunctioning or damage.

;Capacity
;Number of DRAM devices: The number of chips is a multiple of 8 for non-[[Error-correcting code|ECC]] modules and a multiple of 9 for ECC modules. Chips can occupy one side (''single sided'') or both sides (''dual sided'') of the module. The maximal number of chips per DDR module is 36 (9×4) for ECC and 32 (8x4) for non-ECC.
;ECC vs non-ECC: Modules that have [[Error detection and correction#Error-correcting memory|error-correcting code]] are labeled as [[dynamic random-access memory#Error detection and correction|ECC]].  Modules without error correcting code are labeled '''non-ECC'''.
;Timings: [[CAS latency]] (CL), clock cycle time (t<sub>CK</sub>), row cycle time (t<sub>RC</sub>), refresh row cycle time (t<sub>RFC</sub>), row active time (t<sub>RAS</sub>).
;Buffering: [[Registered memory|Registered]] (or buffered) vs [[Unbuffered memory|unbuffered]].
;Packaging: Typically [[DIMM]] or [[SO-DIMM]].
;Power consumption: A test with DDR and DDR2 RAM in 2005 found that average power consumption appeared to be of the [[Order of magnitude|order]] of 1–3&nbsp;W per 512&nbsp;MB module; this increases with clock rate and when in use rather than idling.<ref>[http://www.silentpcreview.com/article265-page4.html Mike Chin: Power Distribution within Six PCs].</ref><!--Out of order and from 2003, but very useful <ref>http://www.overclockers.com/articles696/ {{Dead link|date=February 2022}}</ref>--> A manufacturer has produced calculators to estimate the power used by various types of RAM.<ref>[https://www.micron.com/support/power-calc Micron: System Power Calculators] {{webarchive|url=https://web.archive.org/web/20160126211816/https://www.micron.com/support/power-calc |date=2016-01-26 }}</ref>

Module and chip characteristics are inherently linked.

Total module capacity is a product of one chip's capacity and the number of chips. ECC modules multiply it by {{frac|8|9}} because they use 1&nbsp;bit per byte (8&nbsp;bits) for error correction. A module of any particular size can therefore be assembled either from 32 small chips (36 for ECC memory), or 16(18) or 8(9) bigger ones.

DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip and number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently, a module with a greater number of chips or using ×8 chips instead of ×4 will have more ranks.

{| class="wikitable floatright"
|+ Example: Variations of 1&nbsp;GB PC2100 registered DDR SDRAM module with ECC
! Module<br>size
! Number<br>of chips
! Chip<br>size
! Chip<br>organization
! Number<br>of ranks
|-
| 1 GB
| 36
| 256
| {{0}}64M×4 MBit
| 2
|-
| 1 GB
| 18
| 512
| {{0}}64M×8 MBit
| 2
|-
| 1 GB
| 18
| 512
| 128M×4 MBit
| 1
|}

This example compares different real-world server memory modules with a common size of 1&nbsp;GB. One should definitely be careful buying 1&nbsp;GB memory modules, because all these variations can be sold under one price position without stating whether they are ×4 or ×8, single- or dual-ranked.

There is a common belief that number of module ranks equals number of sides. As above data shows, this is not true. One can also find 2-side/1-rank modules. One can even think of a 1-side/2-rank memory module having 16(18) chips on single side ×8 each, but it is unlikely such a module was ever produced.