Editing Application-specific integrated circuit (section)

== Gate-array and semi-custom design ==
{{Unreferenced section|date=February 2025}}

[[File:S-MOS Systems ASIC SLA6140.jpg|thumb|Microscope photograph of a gate-array ASIC showing the predefined logic cells and custom interconnections. This particular design uses less than 20% of available logic gates.]]

[[Gate array]] design is a manufacturing method in which diffused layers,<ref name="bteng198307">{{ cite journal | url=https://archive.org/details/bte-198307/page/n19/mode/2up | title=The Use of Gate Arrays in Telecommunications | journal=British Telecommunications Engineering | last1=Grierson | first1=J. R. | date=July 1983 | access-date=26 February 2021 | volume=2 | issue=2 | pages=78–80 | issn=0262-401X | quote=In the UK, Ferranti, with their bipolar collector diffused isolation (CDI) arrays, pioneered the commercial use of gate arrays and for many years this was by far the most widely used technology. }}</ref> each consisting of [[transistor]]s and other [[Active element|active devices]], are predefined and [[Wafer (electronics)|electronics wafers]] containing such devices are "held in stock" or unconnected prior to the [[metallizing|metallization]] stage of the [[fabrication process]].  The [[Physical design (electronics)|physical design]] process defines the interconnections of these layers for the final device.  For most ASIC manufacturers, this consists of between two and nine metal layers with each layer running perpendicular to the one below it. Non-recurring engineering costs are much lower than full custom designs, as [[Photolithography|photolithographic]] masks are required only for the metal layers.  Production cycles are much shorter, as metallization is a comparatively quick process; thereby accelerating [[time to market]].

Gate-array ASICs are always a compromise between rapid design and [[Computer performance|performance]] as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% [[circuit utilization]].  Often difficulties in [[Routing (electronic design automation)|routing]] the interconnect require migration onto a larger array device with a consequent increase in the piece part price.  These difficulties are often a result of the layout [[Electronic design automation|EDA]] software used to develop the interconnect.

Pure, logic-only gate-array design is rarely implemented by circuit designers today, having been almost entirely replaced by [[Field-programmability|field-programmable]] devices. The most prominent of such devices are [[field-programmable gate array]]s (FPGAs) which can be programmed by the user and thus offer minimal tooling charges, non-recurring engineering, only marginally increased piece part cost, and comparable performance.

Today, gate arrays are evolving into [[Structured ASIC platform|structured ASICs]] that consist of a large [[IP core]] like a [[central processing unit|CPU]], [[digital signal processor]] units, [[peripheral]]s, standard [[computer bus|interfaces]], integrated [[Computer memory|memories]], [[Static random-access memory|SRAM]], and a block of [[Reconfigurable computing|reconfigurable]], uncommitted logic. This shift is largely because ASIC devices are capable of integrating large blocks of [[Systems engineering|system]] functionality, and [[System on a chip|systems on a chip]] (SoCs) require [[glue logic]], [[Communications system|communications subsystems]] (such as [[Network on a chip|networks on chip]]), [[peripheral]]s, and other components rather than only [[functional unit]]s and basic interconnection.

In their frequent usages in the field, the terms "gate array" and "semi-custom" are synonymous when referring to ASICs. [[Process engineering|Process engineers]] more commonly use the term "semi-custom", while "gate-array" is more commonly used by logic (or gate-level) designers.