Editing X86 (section)

===MMX===
{{Main|MMX (instruction set)}}

MMX is a [[Single instruction, multiple data|SIMD]] instruction set designed by Intel and introduced in 1997 for the [[Pentium MMX]] microprocessor.<ref name="intel">{{cite web |title=Programming With the Intel MMX™ Technology |url=http://www.intel.com/design/intarch/techinfo/pentium/mmxprog.htm |website=Embedded Pentium® Processor Family Technical Information Center |publisher=Intel |access-date=5 June 2022 |archive-url=https://web.archive.org/web/20030725092803/http://www.intel.com/design/intarch/techinfo/pentium/mmxprog.htm |archive-date=25 July 2003 |url-status=dead}}</ref> The MMX instruction set was developed from a similar concept first used on the [[Intel i860]]. It is supported on most subsequent IA-32 processors by Intel and other vendors. MMX is typically used for video processing (in multimedia applications, for instance).<ref>{{cite journal |last1=Krishnaprasad |first1=S. |title=SIMD programming illustrated using Intel's MMX instruction set |journal=Journal of Computing Sciences in Colleges |date=1 January 2004 |volume=19 |issue=3 |pages=268–277 |url=https://dl.acm.org/doi/10.5555/948835.948862 |issn=1937-4771}}</ref>

MMX added 8 new registers to the architecture, known as MM0 through MM7 (henceforth referred to as ''MMn''). In reality, these new registers were just aliases for the existing x87 FPU stack registers. Hence, anything that was done to the floating-point stack would also affect the MMX registers. Unlike the FP stack, these MMn registers were fixed, not relative, and therefore they were randomly accessible. The instruction set did not adopt the stack-like semantics so that existing operating systems could still correctly save and restore the register state when multitasking without modifications.<ref name="intel" />

Each of the MMn registers are 64-bit integers. However, one of the main concepts of the MMX instruction set is the concept of ''packed data types'', which means instead of using the whole register for a single 64-bit integer ([[quadword]]), one may use it to contain two 32-bit integers ([[Integer (computer science)|doubleword]]), four 16-bit integers ([[Integer (computer science)|word]]) or eight 8-bit integers ([[Integer (computer science)|byte]]). Given that the MMX's 64-bit MMn registers are aliased to the FPU stack and each of the floating-point registers are 80&nbsp;bits wide, the upper 16&nbsp;bits of the floating-point registers are unused in MMX. These bits are set to all ones by any MMX instruction, which correspond to the floating-point representation of [[NaN]]s or infinities.<ref name="intel" />