Editing Synchronous dynamic random-access memory (section)

=== Virtual channel memory (VCM) SDRAM ===
VCM was a proprietary type of SDRAM that was designed by [[NEC]], but released as an open standard with no licensing fees. It is pin-compatible with standard SDRAM, but the commands are different. The technology was a potential competitor of [[RDRAM]] because VCM was not nearly as expensive as RDRAM was. A Virtual Channel Memory (VCM) module is mechanically and electrically compatible with standard SDRAM, so support for both depends only on the capabilities of the [[memory controller]]. In the late 1990s, a number of PC [[Northbridge (computing)|northbridge]] chipsets (such as the popular [[List of VIA chipsets#Slot A and Socket A|VIA KX133 and KT133]]) included VCSDRAM support.

VCM inserts an SRAM cache of 16 "channel" buffers, each 1/4 row "segment" in size, between DRAM banks' sense amplifier rows and the data I/O pins. "Prefetch" and "restore" commands, unique to VCSDRAM, copy data between the DRAM's sense amplifier row and the channel buffers, while the equivalent of SDRAM's read and write commands specify a channel number to access. Reads and writes may thus be performed independent of the currently active state of the DRAM array, with the equivalent of four full DRAM rows being "open" for access at a time. This is an improvement over the two open rows possible in a standard two-bank SDRAM. (There is actually a 17th "dummy channel" used for some operations.)

To read from VCSDRAM, after the active command, a "prefetch" command is required to copy data from the sense amplifier array to the channel SDRAM. This command specifies a bank, two bits of column address (to select the segment of the row), and four bits of channel number. Once this is performed, the DRAM array may be precharged while read commands to the channel buffer continue. To write, first the data is written to a channel buffer (typically previous initialized using a Prefetch command), then a restore command, with the same parameters as the prefetch command, copies a segment of data from the channel to the sense amplifier array.

Unlike a normal SDRAM write, which must be performed to an active (open) row, the VCSDRAM bank must be precharged (closed) when the restore command is issued. An active command immediately after the restore command specifies the DRAM row completes the write to the DRAM array. There is, in addition, a 17th "dummy channel" which allows writes to the currently open row. It may not be read from, but may be prefetched to, written to, and restored to the sense amplifier array.<ref>{{Citation |url=https://www.notebookservice030.de/downloads/docs/HYB39V64x0yT.pdf |archive-url=https://web.archive.org/web/20181112021502/https://www.notebookservice030.de/downloads/docs/HYB39V64x0yT.pdf |archive-date=2018-11-12 |url-status=live |title=HYB39V64x0yT 64MBit Virtual Channel SDRAM |author=Siemens Semiconductor Group }}</ref><ref>{{Citation |url=http://www.ic72.com/pdf_file/u/32271.pdf |archive-url=https://web.archive.org/web/20131203022329/http://www.ic72.com/pdf_file/u/32271.pdf |archive-date=2013-12-03 |url-status=live |title=128M-BIT VirtualChannel SDRAM preliminary datasheet |author=NEC |year=1999 |access-date=2012-07-17}}</ref>

Although normally a segment is restored to the same memory address as it was prefetched from, the channel buffers may also be used for very efficient copying or clearing of large, aligned memory blocks. (The use of quarter-row segments is driven by the fact that DRAM cells are narrower than SRAM cells.) The SRAM bits are designed to be four DRAM bits wide, and are conveniently connected to one of the four DRAM bits they straddle.) Additional commands prefetch a pair of segments to a pair of channels, and an optional command combines prefetch, read, and precharge to reduce the overhead of random reads.

The above are the JEDEC-standardized commands. Earlier chips did not support the dummy channel or pair prefetch, and use a different encoding for precharge.

A 13-bit address bus, as illustrated here, is suitable for a device up to 128&nbsp;Mbit{{binpre}}. It has two banks, each containing 8,192 rows and 8,192 columns. Thus, row addresses are 13 bits, segment addresses are two bits, and eight column address bits are required to select one byte from the 2,048 bits (256 bytes) in a segment.