Editing Flash memory (section)

===NOR memories===
[[File:IPhone 3G teardown - Intel 3050M0Y0CE -3303.jpg|thumb|NOR flash by Intel]]
Reading from NOR flash is similar to reading from random-access memory, provided the address and data bus are mapped correctly. Because of this, most microprocessors can use NOR&nbsp;flash memory as [[execute in place]] (XIP) memory,<ref>{{cite book | url=https://books.google.com/books?id=vaq11vKwo_kC&dq=nand+flash+xip&pg=PA12 | title=Inside NAND Flash Memories | isbn=978-90-481-9431-5 | last1=Micheloni | first1=Rino | last2=Crippa | first2=Luca | last3=Marelli | first3=Alessia | date=27 July 2010 | publisher=Springer }}</ref> meaning that programs stored in NOR&nbsp;flash can be executed directly from the NOR&nbsp;flash without needing to be copied into RAM first. NOR&nbsp;flash may be programmed in a random-access manner similar to reading. Programming changes bits from a logical one to a zero. Bits that are already zero are left unchanged. Erasure must happen a block at a time, and resets all the bits in the erased block back to one. Typical block sizes are 64, 128, or 256&nbsp;[[KiB]].

Bad block management is a relatively new feature in NOR&nbsp;chips. In older NOR devices not supporting bad block management, the software or [[device driver]] controlling the memory chip must correct for blocks that wear out, or the device will cease to work reliably.

The specific commands used to lock, unlock, program, or erase NOR memories differ for each manufacturer. To avoid needing unique driver software for every device made, special [[Common Flash Memory Interface]] (CFI) commands allow the device to identify itself and its critical operating parameters.

Besides its use as random-access ROM, NOR&nbsp;flash can also be used as a storage device, by taking advantage of random-access programming. Some devices offer read-while-write functionality so that code continues to execute even while a program or erase operation is occurring in the background. For sequential data writes, NOR&nbsp;flash chips typically have slow write speeds, compared with NAND&nbsp;flash.

Typical NOR flash does not need an [[error correcting code]].<ref name="types_of_ecc">
Spansion.
[http://www.spansion.com/Support/Application%20Notes/Types_of_ECC_Used_on_Flash_AN.pdf "What Types of ECC Should Be Used on Flash Memory?"] {{webarchive|url=https://web.archive.org/web/20160304044226/http://www.spansion.com/Support/Application%20Notes/Types_of_ECC_Used_on_Flash_AN.pdf |date=4 March 2016 }}.
2011.
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