Editing ARM architecture family (section)

===DSP enhancement instructions===
To improve the ARM architecture for [[digital signal processing]] and multimedia applications, DSP instructions were added to the instruction set.<ref>{{cite web |url=https://www.arm.com/products/CPUs/cpu-arch-DSP.html |title=ARM DSP Instruction Set Extensions |website=arm.com |access-date=18 April 2009 |archive-url=https://web.archive.org/web/20090414011837/https://www.arm.com/products/CPUs/cpu-arch-DSP.html |archive-date=14 April 2009 |url-status=live}}</ref> These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures. E-variants also imply T, D, M, and I.

The new instructions are common in [[digital signal processor]] (DSP) architectures. They include variations on signed [[multiply–accumulate operation|multiply–accumulate]], [[saturation arithmetic|saturated add and subtract]], and [[count leading zeros]].

First introduced in 1999, this extension of the core instruction set contrasted with ARM's earlier DSP coprocessor known as Piccolo, which employed a distinct, incompatible instruction set whose execution involved a separate program counter.<ref name="eetimes19990503">{{ cite magazine | url=https://www.eetimes.com/epf-arc-arm-add-dsp-extensions-to-their-risc-cores/ | title=EPF: ARC, ARM add DSP extensions to their RISC cores | website=EE Times | last1=Clarke | first1=Peter | date=3 May 1999 | access-date=15 March 2024 }}</ref> Piccolo instructions employed a distinct register file of sixteen 32-bit registers, with some instructions combining registers for use as 48-bit accumulators and other instructions addressing 16-bit half-registers. Some instructions were able to operate on two such 16-bit values in parallel. Communication with the Piccolo register file involved ''load to Piccolo'' and ''store from Piccolo'' coprocessor instructions via two buffers of eight 32-bit entries. Described as reminiscent of other approaches, notably Hitachi's SH-DSP and Motorola's 68356, Piccolo did not employ dedicated local memory and relied on the bandwidth of the ARM core for DSP operand retrieval, impacting concurrent performance.<ref name="microprocessorreport19961118_piccolo">{{ cite magazine | url=https://www.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/101504.PDF | title=ARM Tunes Piccolo for DSP Performance | magazine=Microprocessor Report | last1=Turley | first1=Jim | date=18 November 1996 | access-date=15 March 2024 }}</ref> Piccolo's distinct instruction set also proved not to be a "good compiler target".<ref name="eetimes19990503"/>