Editing Peripheral Component Interconnect (section)

====Address phase timing====

[[File:AddressPhaseTiming wavedrom.svg]]

Notes:
* GNT# Irrelevant after cycle has started
* Address is only valid for one cycle.
* C/BE will provide the command following by first data phase byte enables

On the rising edge of clock 0, the initiator observes FRAME# and IRDY# both high, and GNT# low, so it drives the address, command, and asserts FRAME# in time for the rising edge of clock 1. Targets latch the address and begin decoding it. They may respond with DEVSEL# in time for clock 2 (fast DEVSEL), 3 (medium) or 4 (slow). Subtractive decode devices, seeing no other response by clock 4, may respond on clock 5. If the master does not see a response by clock 5, it will terminate the transaction and remove FRAME# on clock 6.

TRDY# and STOP# are deasserted (high) during the address phase.  The initiator may assert IRDY# as soon as it is ready to transfer data, which could theoretically be as soon as clock 2.