Editing ARM architecture family (section)

==={{Anchor|CoreSight}}Debugging===
{{More citations needed section|date=March 2011}}
All modern ARM processors include hardware debugging facilities, allowing software debuggers to perform operations such as halting, stepping, and breakpointing of code starting from reset. These facilities are built using [[JTAG]] support, though some newer cores optionally support ARM's own two-wire "SWD" protocol. In ARM7TDMI cores, the "D" represented JTAG debug support, and the "I" represented presence of an "EmbeddedICE" debug module. For ARM7 and ARM9 core generations, EmbeddedICE over JTAG was a de facto debug standard, though not architecturally guaranteed.

The ARMv7 architecture defines basic debug facilities at an architectural level. These include breakpoints, watchpoints and instruction execution in a "Debug Mode"; similar facilities were also available with EmbeddedICE. Both "halt mode" and "monitor" mode debugging are supported. The actual transport mechanism used to access the debug facilities is not architecturally specified, but implementations generally include JTAG support.

There is a separate ARM "CoreSight" debug architecture, which is not architecturally required by ARMv7 processors.

====Debug Access Port====
The Debug Access Port (DAP) is an implementation of an ARM Debug Interface.<ref>
{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0314h/Babdadfc.html |title=CoreSight Components: About the Debug Access Port}}
</ref>
There are two different supported implementations, the Serial Wire [[JTAG]] Debug Port (SWJ-DP) and the Serial Wire Debug Port (SW-DP).<ref>
{{cite web|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0179b/ar01s01s03.html |title=The Cortex-M3: Debug Access Port (DAP)}}
</ref>
CMSIS-DAP is a standard interface that describes how various debugging software on a host PC can communicate over USB to firmware running on a hardware debugger, which in turn talks over SWD or JTAG to a CoreSight-enabled ARM Cortex CPU.<ref>
{{cite web |first=Mike |last=Anderson
|url=https://elinux.org/images/7/7f/Manderson5.pdf |title=Understanding ARM HW Debug Options}}
</ref><ref>
{{cite web |url=http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm |title=CMSIS-DAP Debugger User's Guide}}
</ref><ref>
{{cite web |url=https://www.nimblemachines.com/cmsis-dap/ |title=CMSIS-DAP}}
</ref>