Editing System on a chip (section)

=== Methodologies ===
{{Further|Multi-objective optimization|Multiple-criteria decision analysis|Architecture tradeoff analysis method|label3=Architecture tradeoff analysis}}
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Systems on chip are modeled with standard hardware [[verification and validation]] techniques, but additional techniques are used to model and optimize SoC design alternatives to make the system optimal with respect to [[multiple-criteria decision analysis]] on the above optimization targets.

==== Task scheduling ====
[[Scheduling (computing)|Task scheduling]] is an important activity in any computer system with multiple [[Process (computing)|processes]] or [[Thread (computing)|threads]] sharing a single processor core. It is important to reduce {{Section link||Latency|nopage=y}} and increase {{Section link||Throughput|nopage=y}} for [[embedded software]] running on an SoC's {{Section link||Processor cores|nopage=y}}.  Not every important computing activity in a SoC is performed in software running on on-chip processors, but scheduling can drastically improve performance of software-based tasks and other tasks involving [[shared resource]]s.

Software running on SoCs often schedules tasks according to [[network scheduling]] and [[Stochastic scheduling|randomized scheduling]] algorithms.

==== Pipelining ====
{{Broader|Pipeline (computing)}}
Hardware and software tasks are often pipelined in [[processor design]]. Pipelining is an important principle for [[speedup]] in [[computer architecture]]. They are frequently used in [[GPU]]s ([[graphics pipeline]]) and RISC processors (evolutions of the [[classic RISC pipeline]]), but are also applied to application-specific tasks such as [[digital signal processing]] and multimedia manipulations in the context of SoCs.<ref name=":1" />

==== Probabilistic modeling ====
SoCs are often analyzed though [[probabilistic model]]s, [[Queueing theory#Queueing networks|queueing network]]s, and [[Markov chain]]s. For instance, [[Little's law]] allows SoC states and NoC buffers to be modeled as arrival processes and analyzed through [[Poisson random variable]]s and [[Poisson process]]es.

==== Markov chains ====
SoCs are often modeled with [[Markov chain]]s, both [[Markov chain#Discrete-time Markov chain|discrete time]] and [[Markov chain#Continuous-time Markov chain|continuous time]] variants. Markov chain modeling allows [[asymptotic analysis]] of the SoC's [[Markov chain#Steady-state analysis and limiting distributions|steady state distribution]] of power, heat, latency and other factors to allow design decisions to be optimized for the common case.