Editing System on a chip (section)

==== Latency ====
{{Expand section|date=October 2018}}
SoCs are optimized to minimize [[Latency (engineering)|latency]] for some or all of their functions. This can be accomplished by [[Integrated circuit layout|laying out]] elements with proper proximity and [[Locality of reference|locality]] to each-other to minimize the interconnection delays and maximize the speed at which data is communicated between modules, [[Execution unit|functional units]] and memories. In general, optimizing to minimize latency is an [[NP-completeness|NP-complete]] problem equivalent to the [[Boolean satisfiability problem]].

For [[Task (computing)|tasks]] running on processor cores, latency and throughput can be improved with [[Scheduling (computing)|task scheduling]]. Some tasks run in application-specific hardware units, however, and even task scheduling may not be sufficient to optimize all software-based tasks to meet timing and throughput constraints.