Editing Synchronous dynamic random-access memory (section)

=== DDR4 ===
{{Main|DDR4 SDRAM}}

DDR4 SDRAM is the successor to [[DDR3 SDRAM]]. It was revealed at the [[Intel Developer Forum]] in San Francisco in 2008, and was due to be released to market during 2011. The timing varied considerably during its development - it was originally expected to be released in 2012,<ref>[http://intel.wingateweb.com/US08/published/sessions/MASS006/SF08_MASS006_100s.pdf DDR4 PDF page 23]</ref> and later (during 2010) expected to be released in 2015,<ref>{{cite web|url=http://www.semiaccurate.com/2010/08/16/ddr4-not-expected-until-2015/|title=DDR4 not expected until 2015|work=semiaccurate.com|date=16 August 2010}}</ref> before samples were announced in early 2011 and manufacturers began to announce that commercial production and release to market was anticipated in 2012. DDR4 reached mass market adoption around 2015, which is comparable with the approximately five years taken for DDR3 to achieve mass market transition over DDR2.

The DDR4 chips run at 1.2&nbsp;[[Volt|V]] or less,<ref>{{cite web|url=http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009.html|title=IDF: "DDR3 won't catch up with DDR2 during 2009"|work=Alphr}}</ref><ref>{{cite web|url=http://www.heise-online.co.uk/news/IDF-DDR4-the-successor-to-DDR3-memory--/111367|title=heise online - IT-News, Nachrichten und Hintergründe|work=heise online}}</ref> compared to the 1.5&nbsp;V of DDR3 chips, and have in excess of 2 billion [[data transfer]]s per second. They were expected to be introduced at frequency rates of 2133&nbsp;MHz, estimated to rise to a potential 4266&nbsp;MHz<ref>{{cite web |url=http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html |title=Next-Generation DDR4 Memory to Reach 4.266GHz - Report |date=August 16, 2010 |publisher=Xbitlabs.com |access-date=2011-01-03 |url-status=dead |archive-url=https://web.archive.org/web/20101219085440/http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html |archive-date=December 19, 2010 }}</ref> and lowered voltage of 1.05&nbsp;V<ref>{{cite news|url=http://www.hardware-infos.com/news.php?news=2332|title=IDF: DDR4 memory targeted for 2012|publisher=hardware-infos.com|language=de|access-date=2009-06-16|archive-url=https://web.archive.org/web/20090713025046/http://www.hardware-infos.com/news.php?news=2332|archive-date=2009-07-13|url-status=dead}}</ref> by 2013.

DDR4 did ''not'' double the internal prefetch width again, but uses the same 8''n'' prefetch as DDR3.<ref name="jedec_ddr3_ddr4">{{cite press release |url=http://www.jedec.org/news/pressreleases/jedec-announces-key-attributes-upcoming-ddr4-standard |title=JEDEC Announces Key Attributes of Upcoming DDR4 Standard |publisher=[[JEDEC]] |date=2011-08-22 |access-date=2011-01-06}}</ref> Thus, it will be necessary to interleave reads from several banks to keep the data bus busy.

In February 2009, [[Samsung]] validated 40&nbsp;nm DRAM chips, considered a "significant step" towards DDR4 development<ref>{{cite news |url=http://www.tgdaily.com/content/view/41316/139/ |title=Samsung hints to DDR4 with first validated 40&nbsp;nm DRAM |last=Gruener |first=Wolfgang |date=February 4, 2009 |publisher=tgdaily.com |access-date=2009-06-16 |url-status=dead |archive-url=https://web.archive.org/web/20090524133306/http://www.tgdaily.com/content/view/41316/139/ |archive-date=May 24, 2009 }}</ref> since, as of 2009, current DRAM chips were only beginning to migrate to a 50&nbsp;nm process.<ref>{{cite web |url=http://www.dailytech.com/DDR3+Will+be+Cheaper+Faster+in+2009/article13977.htm |title=DDR3 Will be Cheaper, Faster in 2009 |last=Jansen |first=Ng |date=January 20, 2009 |publisher=dailytech.com |access-date=2009-06-17 |url-status=dead |archive-url=https://web.archive.org/web/20090622084614/http://www.dailytech.com/DDR3+Will+be+Cheaper+Faster+in+2009/article13977.htm |archive-date=June 22, 2009 }}</ref> In January 2011, [[Samsung]] announced the completion and release for testing of a 30&nbsp;nm 2048&nbsp;MB{{binpre}} DDR4 DRAM module. It has a maximum bandwidth of 2.13&nbsp;[[Gbit/s]] at 1.2&nbsp;V, uses [[pseudo open drain]] technology and draws 40% less power than an equivalent DDR3 module.<ref>{{cite web |title=Samsung Develops Industry's First DDR4 DRAM, Using 30nm Class Technology |url=http://www.samsung.com/us/business/semiconductor/newsView.do?news_id=1202 |publisher=Samsung |access-date=2011-03-13 |date=2011-01-04}}</ref><ref>{{cite web |url=http://www.techspot.com/news/41818-samsung-develops-ddr4-memory-up-to-40-more-efficient.html |title=Samsung develops DDR4 memory, up to 40% more efficient |work=TechSpot|date=4 January 2011 }}</ref>