Editing Analog-to-digital converter (section)

===Time-interleaved===
A [[time-interleaved ADC]] uses M parallel ADCs where each ADC samples data every M:th cycle of the effective sample clock. The result is that the sample rate is increased M times compared to what each individual ADC can manage. In practice, the individual differences between the M ADCs degrade the overall performance reducing the [[spurious-free dynamic range]] (SFDR).<ref>{{cite journal|last=Vogel|first=Christian|title=The Impact of Combined Channel Mismatch Effects in Time-interleaved ADCs|journal=IEEE Transactions on Instrumentation and Measurement|year=2005|volume=55|issue=1|pages=415–427|doi=10.1109/TIM.2004.834046|bibcode=2005ITIM...54..415V |citeseerx=10.1.1.212.7539|s2cid=15038020}}</ref> However, techniques exist to correct for these time-interleaving mismatch errors.<ref>{{citation |url=https://www.analog.com/en/analog-dialogue/articles/interleaving-adcs.html |author1=Gabriele Manganaro |author2=David H. Robertson |title=Interleaving ADCs: Unraveling the Mysteries |date=July 2015 |publisher=[[Analog Devices]] |access-date=2021-10-07}}</ref>