Editing System on a chip (section)

==== Waste heat ====
{{Main|Heat generation in integrated circuits}}{{See also|Thermal management (electronics)|Thermal design power|label 1=Thermal management in electronics}}
SoC designs are optimized to minimize [[waste heat]] [[dissipation|output]] on the chip. As with other [[integrated circuit]]s, heat generated due to high [[power density]] are the [[Bottleneck (engineering)|bottleneck]] to further [[miniaturization]] of components.<ref name=":2">{{Cite book|title=Heat Management in Integrated circuits: On-chip and system-level monitoring and cooling|last=Ogrenci-Memik|first=Seda|publisher=The Institution of Engineering and Technology|year=2015|isbn=978-1-84919-935-3|location=London, United Kingdom|oclc=934678500}}</ref>{{Rp|1}} The power densities of high speed integrated circuits, particularly microprocessors and including SoCs, have become highly uneven. Too much waste heat can damage circuits and erode [[Reliability (semiconductor)|reliability]] of the circuit over time. High temperatures and thermal stress negatively impact reliability, [[stress migration]], decreased [[mean time between failures]], [[electromigration]], [[wire bonding]], [[Metastability (electronics)|metastability]] and other performance degradation of the SoC over time.<ref name=":2" />{{Rp|2–9}}

In particular, most SoCs are in a small physical area or volume and therefore the effects of waste heat are compounded because there is little room for it to diffuse out of the system. Because of high [[transistor count]]s on modern devices, oftentimes a layout of sufficient throughput and high [[Transistors density|transistor density]] is physically realizable from [[Semiconductor device fabrication|fabrication processes]] but would result in unacceptably high amounts of heat in the circuit's volume.<ref name=":2" />{{Rp|1}}

These thermal effects force SoC and other chip designers to apply conservative [[design margin]]s, creating less performant devices to mitigate the risk of [[catastrophic failure]]. Due to increased [[Transistors density|transistor densities]] as length scales get smaller, each [[Semiconductor node|process generation]] produces more heat output than the last. Compounding this problem, SoC architectures are usually heterogeneous, creating spatially inhomogeneous [[heat flux]]es, which cannot be effectively mitigated by uniform [[passive cooling]].<ref name=":2" />{{Rp|1}}