Editing ARM architecture family (section)

====Registers====
{| class="wikitable" style="float: right; margin-left: 1.5em; margin-right: 0; margin-top: 0;"
|+ Registers across CPU modes
|-
! usr !! sys !! svc !! abt !! und !! [[Interrupt request|irq]] !! [[Fast interrupt request|fiq]]
|-
| colspan="7" style="text-align:center;"| R0
|-
| colspan="7" style="text-align:center;"| R1
|-
| colspan="7" style="text-align:center;"| R2
|-
| colspan="7" style="text-align:center;"| R3
|-
| colspan="7" style="text-align:center;"| R4
|-
| colspan="7" style="text-align:center;"| R5
|-
| colspan="7" style="text-align:center;"| R6
|-
| colspan="7" style="text-align:center;"| R7
|- align=center
| colspan=6 | R8 || R8_fiq
|- align=center
| colspan=6 | R9 || R9_fiq
|- align=center
| colspan=6 | R10 || R10_fiq
|- align=center
| colspan=6 | R11 || R11_fiq
|- align=center
| colspan=6 | R12 || R12_fiq
|- align=center
| colspan=2 | R13 || R13_svc || R13_abt || R13_und || R13_irq || R13_fiq
|- align=center
| colspan=2 | R14 || R14_svc || R14_abt || R14_und || R14_irq || R14_fiq
|-
| colspan="7" style="text-align:center;"| R15
|-
| colspan="7" style="text-align:center;"| CPSR
|- align=center
| colspan=2 | || SPSR_svc || SPSR_abt || SPSR_und || SPSR_irq || SPSR_fiq
|}

Registers R0 through R7 are the same across all CPU modes; they are never banked.

Registers R8 through R12 are the same across all CPU modes except FIQ mode.  FIQ mode has its own distinct R8 through R12 registers.

R13 and R14 are banked across all privileged CPU modes except system mode. That is, each mode that can be entered because of an exception has its own R13 and R14. These registers generally contain the stack pointer and the return address from function calls, respectively.

Aliases:
* R13 is also referred to as SP, the [[stack pointer]].
* R14 is also referred to as LR, the [[link register]].
* R15 is also referred to as PC, the [[program counter]].

The Current Program Status Register (CPSR) has the following 32&nbsp;bits.<ref>{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/I27695.html |title=ARM Information Center |access-date=10 July 2015}}</ref>
* M (bits 0–4) is the processor mode bits.
* T (bit 5) is the Thumb state bit.
* F (bit 6) is the FIQ disable bit.
* I (bit 7) is the IRQ disable bit.
* A (bit 8) is the imprecise data abort disable bit.
* E (bit 9) is the data endianness bit.
* IT (bits 10–15 and 25–26) is the if-then state bits.
* GE (bits 16–19) is the greater-than-or-equal-to bits.
* DNM (bits 20–23) is the do not modify bits.
* J (bit 24) is the Java state bit.
* Q (bit 27) is the sticky overflow bit.
* V (bit 28) is the overflow bit.
* C (bit 29) is the carry/borrow/extend bit.
* Z (bit 30) is the zero bit.
* N (bit 31) is the negative/less than bit.