Editing X86 (section)

==Operating modes==

===Real mode===
{{Main|Real mode}}
{{More citations needed section|date=January 2014}}

Real Address mode,<ref>{{cite book|url=http://bitsavers.org/components/intel/80286/210498-001_iAPX_286_Programmers_Reference_1983.pdf|title=iAPX 286 Programmer's Reference|at=Section 1.2, "Modes of Operation"|publisher=Intel|year=1983|access-date=January 27, 2014|archive-date=August 28, 2017|archive-url=https://web.archive.org/web/20170828232803/http://www.bitsavers.org/components/intel/80286/210498-001_iAPX_286_Programmers_Reference_1983.pdf|url-status=live}}</ref> commonly called Real mode, is an operating mode of [[8086]] and later x86-compatible [[Central processing unit|CPUs]]. Real mode is characterized by a 20-bit segmented memory address space (meaning that only slightly more than 1 [[Mebibyte|MiB]] of memory can be addressed{{Efn|Because a segmented address is the sum of a 16-bit segment multiplied by 16 and a 16-bit offset, the maximum address is 1,114,095 (10FFEF&nbsp;hex), for an addressability of 1,114,096&nbsp;bytes&nbsp;{{=}} 1&nbsp;MB&nbsp;+ 65,520&nbsp;bytes. Before the 80286, x86 CPUs had only 20 physical address lines (address bit signals), so the 21st bit of the address, bit 20, was dropped and addresses past 1&nbsp;MB were mirrors of the low end of the address space (starting from address zero). Since the 80286, all x86 CPUs have at least 24 physical address lines, and bit 20 of the computed address is brought out onto the address bus in real mode, allowing the CPU to address the full 1,114,096 bytes reachable with an x86 segmented address. On the popular IBM PC platform, switchable hardware to disable the 21st address bit was added to machines with an 80286 or later so that all programs designed for 8088/8086-based models could run, while newer software could take advantage of the "high" memory in real mode and the full 16&nbsp;MB or larger address space in protected mode—see A20 gate.}}), direct software access to peripheral hardware, and no concept of [[memory protection]] or [[computer multitasking|multitasking]] at the hardware level. All x86 CPUs in the [[Intel 80286|80286]] series and later start up in real mode at power-on; [[Intel 80186|80186]] CPUs and earlier had only one operational mode, which is equivalent to real mode in later chips. (On the IBM PC platform, direct software access to the IBM [[BIOS]] routines is available only in real mode, since BIOS is written for real mode. However, this is not a property of the x86 CPU but of the IBM BIOS design.)

In order to use more than 64&nbsp;KB of memory, the segment registers must be used. This created great complications for compiler implementors who introduced odd pointer modes such as "near", "far" and "huge" to leverage the implicit nature of segmented architecture to different degrees, with some pointers containing 16-bit offsets within implied segments and other pointers containing segment addresses and offsets within segments. It is technically possible to use up to 256&nbsp;KB of memory for code and data, with up to 64&nbsp;KB for code, by setting all four segment registers once and then only using 16-bit offsets (optionally with default-segment override prefixes) to address memory, but this puts substantial restrictions on the way data can be addressed and memory operands can be combined, and it violates the architectural intent of the Intel designers, which is for separate data items (e.g. arrays, structures, code units) to be contained in separate segments and addressed by their own segment addresses, in new programs that are not ported from earlier 8-bit processors with 16-bit address spaces.

===Unreal mode===
{{Main|Unreal mode}}
Unreal mode is used by some 16-bit [[operating system]]s and some 32-bit [[boot loader]]s.

===System Management Mode===
{{See also|System Management Mode}}
The System Management Mode (SMM) is only used by the system firmware ([[BIOS]]/[[UEFI]]), not by [[operating system]]s and applications software. The SMM code is running in SMRAM.

===Protected mode===
{{Main|Protected mode}}
{{More citations needed section|date=January 2014}}

In addition to real mode, the Intel 80286 supports protected mode, expanding addressable [[physical memory]] to 16 [[megabyte|MB]] and addressable [[virtual memory]] to 1&nbsp;[[gigabyte|GB]], and providing [[protected memory]], which prevents programs from corrupting one another. This is done by using the segment registers only for storing an index into a descriptor table that is stored in memory. There are two such tables, the [[Global Descriptor Table]] (GDT) and the [[Local Descriptor Table]] (LDT), each holding up to 8192 segment descriptors, each segment giving access to 64&nbsp;KB of memory. In the 80286, a segment descriptor provides a 24-bit [[base address]], and this base address is added to a 16-bit offset to create an absolute address. The base address from the table fulfills the same role that the literal value of the segment register fulfills in real mode; the segment registers have been converted from direct registers to indirect registers. Each segment can be assigned one of four [[ring (computer security)|ring]] levels used for hardware-based [[computer security]]. Each segment descriptor also contains a segment limit field which specifies the maximum offset that may be used with the segment. Because offsets are 16 bits, segments are still limited to 64&nbsp;KB each in 80286 protected mode.<ref>{{cite book|year=1983|url=http://bitsavers.org/components/intel/80286/210498-001_iAPX_286_Programmers_Reference_1983.pdf|title=iAPX 286 Programmer's Reference|at=Chapter 6, "Memory Management and Virtual Addressing"|publisher=Intel|access-date=January 27, 2014|archive-date=August 28, 2017|archive-url=https://web.archive.org/web/20170828232803/http://www.bitsavers.org/components/intel/80286/210498-001_iAPX_286_Programmers_Reference_1983.pdf|url-status=live}}</ref>

Each time a segment register is loaded in protected mode, the 80286 must read a 6-byte segment descriptor from memory into a set of hidden internal registers. Thus, loading segment registers is much slower in protected mode than in real mode, and changing segments very frequently is to be avoided. Actual memory operations using protected mode segments are not slowed much because the 80286 and later have hardware to check the offset against the segment limit in parallel with instruction execution.

The [[Intel 80386]] extended offsets and also the segment limit field in each segment descriptor to 32 bits, enabling a segment to span the entire memory space. It also introduced support in protected mode for [[paging]], a mechanism making it possible to use paged [[virtual memory]] (with 4&nbsp;KB page size). Paging allows the CPU to map any page of the virtual memory space to any page of the physical memory space. To do this, it uses additional mapping tables in memory called page tables. Protected mode on the 80386 can operate with paging either enabled or disabled; the segmentation mechanism is always active and generates virtual addresses that are then mapped by the paging mechanism if it is enabled. The segmentation mechanism can also be effectively disabled by setting all segments to have a base address of 0 and size limit equal to the whole address space; this also requires a minimally-sized segment descriptor table of only four descriptors (since the FS and GS segments need not be used).{{Efn|An extra descriptor record at the top of the table is also required, because the table starts at zero but the minimum descriptor index that can be loaded into a segment register is 1; the value 0 is reserved to represent a segment register that points to no segment.}}

Paging is used extensively by modern multitasking operating systems. [[Linux]], [[386BSD]] and [[Windows NT]] were developed for the 386 because it was the first Intel architecture CPU to support paging and 32-bit segment offsets. The 386 architecture became the basis of all further development in the x86 series.

x86 processors that support protected mode boot into [[real mode]] for backward compatibility with the older 8086 class of processors. Upon power-on (a.k.a. [[booting]]), the processor initializes in real mode, and then begins executing instructions. Operating system boot code, which might be stored in [[read-only memory]], may place the processor into the [[protected mode]] to enable paging and other features. Conversely, segment arithmetic, a common practice in real mode code, is not allowed in protected mode.

====Virtual 8086 mode====
{{Main|Virtual 8086 mode}}

There is also a sub-mode of operation in 32-bit protected mode (a.k.a. 80386 protected mode) called ''[[virtual 8086 mode]]'', also known as ''V86 mode''. This is basically a special hybrid operating mode that allows real mode programs and operating systems to run while under the control of a protected mode supervisor operating system. This allows for a great deal of flexibility in running both protected mode programs and real mode programs simultaneously. This mode is exclusively available for the 32-bit version of protected mode; it does not exist in the 16-bit version of protected mode, or in long mode.

===Long mode===
{{Main|Long mode}}

In the mid 1990s, it was obvious that the 32-bit address space of the x86 architecture was limiting its performance in applications requiring large data sets. A 32-bit address space would allow the processor to directly address only 4&nbsp;GB of data, a size surpassed by applications such as [[Video editing software|video processing]] and [[database engine]]s. Using 64-bit addresses, it is possible to directly address 16&nbsp;[[Exbibyte|EiB]] of data, although most 64-bit architectures do not support access to the full 64-bit address space; for example, AMD64 supports only 48&nbsp;bits from a 64-bit address, split into four paging levels.

In 1999, [[AMD]] published a (nearly) complete specification for a [[64-bit computing|64-bit]] extension of the x86 architecture which they called ''x86-64'' with claimed intentions to produce. That design is currently used in almost all x86 processors, with some exceptions intended for [[embedded system]]s.

Mass-produced ''x86-64'' chips for the general market were available four years later, in 2003, after the time was spent for working prototypes to be tested and refined; about the same time, the initial name ''x86-64'' was changed to ''AMD64''. The success of the AMD64 line of processors coupled with lukewarm reception of the IA-64 architecture forced Intel to release its own implementation of the AMD64 instruction set. Intel had previously implemented support for AMD64<ref>{{Cite web |url=http://www.geek.com/intels-yamhill-technology-x86-64-compatible/ |title=Intel's Yamhill Technology: x86-64 compatible {{!}}Geek.com<!-- Bot generated title --> |access-date=July 18, 2008 |archive-date=September 5, 2012 |archive-url=https://archive.today/20120905073732/http://www.geek.com/intels-yamhill-technology-x86-64-compatible/ |url-status=dead }}</ref> but opted not to enable it in hopes that AMD would not bring AMD64 to market before Itanium's new IA-64 instruction set was widely adopted. It branded its implementation of AMD64 as ''EM64T'', and later rebranded it ''Intel 64''.

In its literature and product version names, Microsoft and Sun refer to AMD64/Intel 64 collectively as ''x64'' in the Windows and [[Solaris (operating system)|Solaris]] operating systems. [[Linux distribution]]s refer to it either as "x86-64", its variant "x86_64", or "amd64". [[Berkeley Software Distribution|BSD]] systems use "amd64" while [[macOS]] uses "x86_64".

Long mode is mostly an extension of the 32-bit instruction set, but unlike the 16–to–32-bit transition, many instructions were dropped in the 64-bit mode. This does not affect actual binary backward compatibility (which would execute legacy code in other modes that retain support for those instructions), but it changes the way assembler and compilers for new code have to work.

This was the first time that a major extension of the x86 architecture was initiated and originated by a manufacturer other than Intel. It was also the first time that Intel accepted technology of this nature from an outside source.