Editing Counter (digital) (section)

===General model===

Digital counters are typically implemented as [[Moore machine]]s because their outputs are determined solely by the current state.<ref name="Kime">{{cite book |last1=Mano |first1=M. Morris |last2=Kime |first2=Charles R. |title=Logic and Computer Design Fundamentals |date=2007 |publisher=Prentice Hall |isbn=978-0131989269}}</ref> This makes counters a natural fit for Moore machines, which in turn simplifies the design and promotes reliable operation.<ref name="Mano">{{cite book |last1=Mano |first1=M. Morris |last2=Ciletti |first2=Michael D. |title=Digital Design |date=2012 |publisher=Prentice Hall |isbn=0132774208 |edition=5th}}</ref>

More specifically, counters are most commonly implemented as Medvedev state machines, a subclass of Moore machines which directly output the current state, with each state naturally encoding a specific count value.<ref name="Nerode">{{cite book |last1=Khoussainov |last2=Nerode |title=Automata Theory and its Applications |date=2001 |publisher=Springer |isbn=978-0-8176-4207-5}}</ref> Since the state register of such machines is directly connected to the counter outputs, encoding logic is not needed and output delays are minimized.

{{multiple image
 | align = none
 | total_width = 700
 | image_gap = 20
 | header = Typical architectures of digital counters

 | image1 = Digital counter in Medvedev FSM.svg
 | alt1 = Medvedev machine
 | caption1 = General model of a counter implemented as a Medvedev machine. Most counters are based on this model.<ref name="Nerode"/>

 | image2 = Digital counter in full Moore FSM.svg
 | alt2 = Full Moore machine
 | caption2 = General model of a counter implemented as a full Moore machine, with output encoding logic between state register and counter outputs
}}

Some counters employ combinational logic between state register and counter outputs to transform the state to a particular output encoding, and thus are classified as full Moore machines. For example, the CMOS 4017 integrated circuit encodes the output of a Johnson decade counter into one-hot format, taking advantage of the Johnson counter's inherent Gray code output to avoid glitches on the one-hot outputs.

<gallery heights="200px" widths="350px">
File:4017 Functional Diagram.svg|Functional diagram of a CMOS 4017 IC, which combines a 5-bit Johnson counter and output decoder logic to implement a cascadable one-hot decade counter
File:CMOS 4017 Diagram Logic Edge Up recadré v1.00.svg|Internal logic of a CMOS 4017 IC; one output is active per state. The two gates at the top facilitate automatic recovery from illegal states.
</gallery>