Editing Visual Instruction Set (section)

== Differences vs x86 ==
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VIS is not an instruction toolkit like [[Intel]]'s MMX and SSE. MMX has only 8 registers shared with the [[Floating-point unit|FPU]] stack, while SPARC processors have 32 registers, also aliased to the double-precision (64-bit) floating point registers.

As with the SIMD instruction set extensions on other [[RISC]] processors, VIS strictly conforms to the main principle of RISC: keep the instruction set concise and efficient.

This design is very different from comparable extensions on [[Complex instruction set computer|CISC]] processors, such as [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4]], [[3DNow!]].

Sometimes, programmers must use several VIS instructions to accomplish an operation that can be done with only one [[MMX (instruction set)|MMX]] or [[Streaming SIMD Extensions|SSE]] instruction, but it should be kept in mind that fewer instructions do not automatically result in better performance.