Editing Very long instruction word (section)

== Motivation ==

A processor that executes every instruction one after the other (i.e., a non-[[instruction pipelining|pipelined]] scalar architecture) may use processor resources inefficiently, yielding potential poor performance. The performance can be improved by executing different substeps of sequential instructions simultaneously (termed ''pipelining''), or even executing multiple instructions entirely simultaneously as in [[superscalar]] architectures. Further improvement can be achieved by executing instructions in an order different from that in which they occur in a program, termed [[out-of-order execution]].<ref name=":0" />

These three methods all raise hardware complexity. Before executing any operations in parallel, the processor must verify that the instructions have no [[dependence analysis|interdependencies]]. For example, if a first instruction's result is used as a second instruction's input, then they cannot execute at the same time and the second instruction cannot execute before the first. Modern out-of-order processors have increased the hardware resources which schedule instructions and determine interdependencies.

In contrast, VLIW executes operations in parallel, based on a fixed schedule, determined when programs are [[compiler|compiled]]. Since determining the order of execution of operations (including which operations can execute simultaneously) is handled by the compiler, the processor does not need the scheduling hardware that the three methods described above require. Thus, VLIW CPUs offer more computing with less hardware complexity (but greater compiler complexity) than do most superscalar CPUs.<ref name=":0" /> This is also complementary to the idea that as many computations as possible should be done before the program is executed, at compile time.