Editing SuperH (section)

===SH-1 and SH-2===
[[Image:HD6417095 01.jpg|150px|thumb|SH-2 on Sega 32X and Sega Saturn]]
The SuperH processor core family was first developed by [[Hitachi]] in the early 1990s. The design concept was for a single [[instruction set]] (ISA) that would be [[upward compatible]] across a series of [[CPU core]]s.

In the past, this sort of design problem would have been solved using [[microcode]], with the low-end models in the series performing non-implemented instructions as a series of more basic instructions. For instance, a "long multiply" (multiplying two 32-bit registers to produce a 64-bit product) might be implemented in hardware on high-end models but instead be performed as a series of additions on low-end models.

One of the key realizations during the development of the [[RISC]] concept was that the microcode had a finite decoding time, and as processors became faster, this represented an unacceptable performance overhead. To address this, Hitachi instead developed a single ISA for the entire line, with unsupported instructions causing traps on those implementations that didn't include hardware support. For instance, the initial models in the line, the SH-1 and SH-2, differed only in their support for 64-bit multiplication; the SH-2 supported {{code|MUL}}, {{code|DMULS}} and {{code|DMULU}}, whereas the SH-1 would cause a trap if these were encountered.{{sfn|Program|1996|p=1}}

The SH-1 was the basic model, supporting a total of 56 instructions. The SH-2 added 64-bit multiplication and a few additional commands for branching and other duties, bringing the total to 62 supported instructions.{{sfn|Program|1996|p=1}} The SH-1 and the SH-2 were used in the [[Sega Saturn]], [[Sega 32X]] and [[Capcom CPS-3]].<ref>{{cite web |title=CP System III (CPS3) Hardware (Capcom) |url=https://www.system16.com/hardware.php?id=799 |website=www.system16.com |publisher=System 16 |access-date=3 August 2019}}</ref>

The ISA uses [[16-bit]] instructions for better code density than 32-bit instructions, which was important at the time due to the high cost of [[DRAM|main memory]] and the implementation cost of cache. As of 2023, code density is still important for small embedded systems and massively multicore processors. The downsides to this approach were that there were fewer bits available to encode a register number or a constant value. In the original SuperH ISA, there were only 16 general registers, requiring four bits for the source and another four for the destination; however some instructions have an implied R0, R15, or a system register as an extra operand. The instruction opcode is four, eight, twelve, or sixteen bits long, and the remaining four-bit fields are used for register or immediate operands in various ways: there are twelve classes of instructions, for a total of 142 instructions in SH-2.{{sfn|Program|1996|pp=30-33}}

Delayed branches are introduced for both SH-1 and SH-2. Unconditional branch instructions have one [[delay slot]].<ref>{{cite web |url=https://www.renesas.com/us/en/document/mah/superh-risc-engine-sh7020-and-sh7021-hd6437020-hd6477021-hd6437021-hd6417021?r=469371 |page=19,48 |title=SH7020 and SH7021 Hardware ManualSuperH™ RISC engine |accessdate=2023-12-02}}</ref>