Editing Shift register (section)

=== Destructive readout ===
{| class="wikitable floatright" style="text-align:center"
|+ Sample usage of a 4-bit shift register. Data input is 10110000.
! {{vert header|Time}}
! {{vert header|Clock }}
! {{vert header|Output 1}}
! {{vert header|Output 2}}
! {{vert header|Output 3}}
! {{vert header|Output 4}}
|-
! 0
| 0 || 0 || 0 || 0 || 0
|-
! 1
| 1 || 1 || 0 || 0 || 0
|-
! 2
| 0 || 0 || 1 || 0 || 0
|-
! 3
| 1 || 1 || 0 || 1 || 0
|-
! 4
| 0 || 1 || 1 || 0 || 1
|-
! 5
| 1 || 0 || 1 || 1 || 0
|-
! 6
| 0 || 0 || 0 || 1 || 1
|-
! 7
| 1 || 0 || 0 || 0 || 1 
|-
! 8
| 0 || 0 || 0 || 0
|}

These are the simplest kind of shift registers. The data string is presented at "data in" and is shifted right one stage each time "data advance" is brought [[Logic level|high]]. At each advance, the bit on the far left (i.e. "data in") is shifted into the first [[flip-flop (electronics)|flip-flop]]'s output. The bit on the far right (i.e. "data out") is shifted out and lost.

The data is stored after each on the "Q" output, so there are four storage "slots" available in this arrangement, hence it is a 4-bit register. To give an idea of the shifting pattern, imagine that the register holds 0000 (so all storage slots are empty). As "data in" presents 1,0,1,1,0,0,0,0 (in that order, with a pulse at "data advance" each time—this is called clocking or strobing) to the register, this is the result. The right hand column corresponds to the right-most flip-flop's output pin, and so on.

So the serial output of the entire value is 00010110. It can be seen that if data were to be continued to input, it would get exactly what was put in (10110000), but offset by four "data advance" cycles. This arrangement is the hardware equivalent of a [[Queue (data structure)|queue]]. Also, at any time, the whole register can be set to zero by bringing the reset (R) pins high.

This arrangement performs ''destructive readout''{{snd}} each datum is lost once it has been shifted out of the right-most bit.