Editing Semiconductor device fabrication (section)

==History==
{{See also|List of semiconductor scale examples|Moore's law|MOS integrated circuit|Semiconductor industry|Transistor density}}

===20th century===
[[File:1957(Figure 9)-Gate oxide transistor by Frosch and Derrick.png|thumb|245x245px|A diagram of the semiconductor oxide transistors made by Frosch and Derick in 1957<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650}}</ref>]]
In 1955, [[Carl Frosch]] and Lincoln Derick, working at [[Bell Telephone Laboratories]], accidentally grew a layer of silicon dioxide over the silicon wafer, for which they observed surface passivation effects.<ref name=":0">{{Cite journal |last1=Huff |first1=Howard |last2=Riordan |first2=Michael |date=2007-09-01 |title=Frosch and Derick: Fifty Years Later (Foreword) |url=https://iopscience.iop.org/article/10.1149/2.F02073IF |journal=The Electrochemical Society Interface |volume=16 |issue=3 |pages=29 |doi=10.1149/2.F02073IF |issn=1064-8208}}</ref><ref>{{Cite patent|number=US2802760A|title=Oxidation of semiconductive surfaces for controlled diffusion|gdate=1957-08-13|invent1=Lincoln|invent2=Frosch|inventor1-first=Derick|inventor2-first=Carl J.|url=https://patents.google.com/patent/US2802760A}}</ref> By 1957 Frosch and Derick, using masking and predeposition, were able to manufacture silicon dioxide transistors; the first planar field effect transistors, in which drain and source were adjacent at the same surface.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650}}</ref> At Bell Labs, the importance of their discoveries was immediately realized. Memos describing the results of their work circulated around Bell Labs before being formally published in 1957. At [[Shockley Semiconductor Laboratory|Shockley Semiconductor]], Shockley had circulated the preprint of their article in December 1956 to all his senior staff, including [[Jean Hoerni]],<ref name="Moskowitz">{{cite book |last1=Moskowitz |first1=Sanford L. |url=https://books.google.com/books?id=2STRDAAAQBAJ&pg=PA168 |title=Advanced Materials Innovation: Managing Global Technology in the 21st century |date=2016 |publisher=[[John Wiley & Sons]] |isbn=978-0-470-50892-3 |page=168}}</ref><ref>{{cite book |author1=Christophe Lécuyer |url=https://books.google.com/books?id=LaZpUpkG70QC&pg=PA62 |title=Makers of the Microchip: A Documentary History of Fairchild Semiconductor |author2=David C. Brook |author3=Jay Last |date=2010 |publisher=MIT Press |isbn=978-0-262-01424-3 |pages=62–63}}</ref><ref>{{cite book |last1=Claeys |first1=Cor L. |url=https://books.google.com/books?id=bu22JNYbE5MC&pg=PA27 |title=ULSI Process Integration III: Proceedings of the International Symposium |date=2003 |publisher=[[The Electrochemical Society]] |isbn=978-1-56677-376-8 |pages=27–30}}</ref><ref name="Lojek120">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |page=120}}</ref> who would later invent the [[planar process]] in 1959 while at [[Fairchild Semiconductor]].<ref>{{patent|US|3025589|Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959}}</ref><ref>{{patent|US|3064167|Hoerni, J. A.: "Semiconductor device" filed May 15, 1960}}</ref>

In 1948, Bardeen patented an insulated-gate transistor (IGFET) with an inversion layer; Bardeen's concept forms the basis of [[MOSFET]] technology today.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> An improved type of MOSFET technology, [[CMOS]], was developed by [[Chih-Tang Sah]] and [[Frank Wanlass]] at [[Fairchild Semiconductor]] in 1963.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019 |archive-date=23 July 2019 |archive-url=https://web.archive.org/web/20190723142758/https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |url-status=live }}</ref><ref>{{cite conference |last1=Sah |first1=Chih-Tang |author1-link=Chih-Tang Sah |last2=Wanlass |first2=Frank |book-title=1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |title=Nanowatt logic using field-effect metal-oxide semiconductor triodes |author2-link=Frank Wanlass |date=February 1963 |volume=VI |pages=32–33 |doi=10.1109/ISSCC.1963.1157450}}</ref> CMOS was commercialised by [[RCA]] in the late 1960s.<ref name="computerhistory1963" /> RCA commercially used CMOS for its [[4000-series integrated circuits]] in 1968, starting with a 20{{nbsp}}μm process before gradually scaling to a [[10 μm process]] over the next several years.<ref name="Lojek330">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |page=330 |url=https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA330 |access-date=2019-07-21 |archive-date=2020-08-06 |archive-url=https://web.archive.org/web/20200806021239/https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA330 |url-status=live }}</ref> Many early semiconductor device manufacturers developed and built their own equipment such as ion implanters.<ref name="ion-implantation-in-silicon-technology">{{cite journal |url=https://www.axcelis.com/wp-content/uploads/2019/02/Ion_Implantation_in_Silicon_Technology.pdf |title=Ion Implantation in Silicon Technology |first1=Leonard |last1=Rubin |first2=John |last2=Poate |journal=The Industrial Physicist |volume=9 |issue=3 |date=June–July 2003 |publisher=[[American Institute of Physics]] |pages=12–15}}</ref>

In 1963, [[Harold M. Manasevit]] was the first to document epitaxial growth of [[silicon on sapphire]] while working at the [[Autonetics]] division of [[North American Aviation]] (now [[Boeing]]). In 1964, he published his findings with colleague William Simpson in the ''Journal of Applied Physics''.<ref name="Manasevit_1964">{{cite journal |last1=Manasevit |first1=H. M. |last2=Simpson |first2=W. J. |title=Single-Crystal Silicon on a Sapphire Substrate |journal=[[Journal of Applied Physics]] |year=1964 |volume=35 |issue=4 |pages=1349–51 |doi=10.1063/1.1713618|bibcode=1964JAP....35.1349M }}</ref> In 1965, C.W. Mueller and P.H. Robinson fabricated a MOSFET (metal–oxide–semiconductor field-effect transistor) using the silicon-on-sapphire process at [[RCA Laboratories]].<ref>{{cite journal |last1=Mueller |first1=C. W. |last2=Robinson |first2=P. H. |title=Grown-film silicon transistors on sapphire |journal=[[Proceedings of the IEEE]] |date=December 1964 |volume=52 |issue=12 |pages=1487–90 |doi=10.1109/PROC.1964.3436}}</ref>

Semiconductor device manufacturing has since spread from [[Texas]] and [[California]] in the 1960s to the rest of the world, including [[Asia]], [[Europe]], and the [[Middle East]]. 

Wafer size has grown over time, from 25&nbsp;mm (1 inch) in 1960, to 50&nbsp;mm (2 inches) in 1969, 100&nbsp;mm (4 inches) in 1976, 125&nbsp;mm (5 inches) in 1981, 150&nbsp;mm (6 inches) in 1983 and 200&nbsp;mm in 1992.<ref>{{cite book | url=https://books.google.com/books?id=NEkPEAAAQBAJ&dq=wafer+size+increase+over+time&pg=PA35 | isbn=978-1-351-24866-2 | title=Extending Moore's Law through Advanced Semiconductor Design and Processing Techniques | date=13 September 2018 | publisher=CRC Press }}</ref><ref>{{cite web | url=https://f450c.org/infographic/ | archive-url=https://web.archive.org/web/20151222155518/http://www.f450c.org/infographic/ | url-status=usurped | archive-date=December 22, 2015 | title=Evolution of the Silicon Wafer Infographic }}</ref>

In the era of 2-inch wafers, these were handled manually using tweezers and held manually for the time required for a given process. Tweezers were replaced by vacuum wands as they generate fewer particles<ref>{{cite book | url=https://books.google.com/books?id=iWTxDwAAQBAJ&dq=wafer+vacuum+wand&pg=PA148 | isbn=978-3-030-40021-7 | title=How Transistor Area Shrank by 1 Million Fold | date=15 July 2020 | publisher=Springer }}</ref> which can contaminate the wafers. Wafer carriers or cassettes, which can hold several wafers at once, were developed to carry several wafers between process steps, but wafers had to be individually removed from the carrier, processed and returned to the carrier, so acid-resistant carriers were developed to eliminate this time consuming process, so the entire cassette with wafers was dipped into wet etching and wet cleaning tanks. When wafer sizes increased to 100&nbsp;mm, the entire cassette would often not be dipped as uniformly, and the quality of the results across the wafer became hard to control. By the time 150&nbsp;mm wafers arrived, the cassettes were not dipped and were only used as wafer carriers and holders to store wafers, and robotics became prevalent for handling wafers. With 200&nbsp;mm wafers manual handling of wafer cassettes becomes risky as they are heavier.<ref>{{cite book | url=https://books.google.com/books?id=Md1-mZ69qMQC&dq=Wafer+box+cassette&pg=PA144 | isbn=978-0-7923-9619-2 | title=Wafer Fabrication: Factory Performance and Analysis | date=30 November 1995 | publisher=Springer }}</ref>

In the 1970s and 1980s, several companies migrated their semiconductor manufacturing technology from [[bipolar junction transistor|bipolar]] to MOSFET technology. Semiconductor manufacturing equipment has been considered costly since 1978.<ref>{{cite web | url=https://www.chiphistory.org/724-semiconductor-equipment-too-expensive-circa-1978 | title=Wafer fab costs skyrocketing out of control }}</ref><ref>https://ieeexplore.ieee.org/document/10569131</ref><ref>https://www.electronicdesign.com/technologies/power/article/21801160/igbts-or-mosfets-which-is-better-for-your-design</ref><ref>https://spectrum.ieee.org/the-future-of-transistors</ref>

In 1984, [[KLA Corporation|KLA]] developed the first automatic reticle and photomask inspection tool.<ref>{{cite web | url=https://www.chiphistory.org/682-kla-200-series-reticle-inspection-systems | title=Kla 200 Series }}</ref> In 1985, KLA developed an automatic inspection tool for silicon wafers, which replaced manual microscope inspection.<ref>{{cite web | url=https://www.chiphistory.org/235-kla-tencor-kla-2020 | title=KLA 2020 - the tool that sparked the yield management revolution }}</ref>

In 1985, SGS (now [[STmicroelectronics]]) invented BCD, also called [[BCDMOS]], a semiconductor manufacturing process using bipolar, CMOS and [[DMOS]] devices.<ref>{{Cite web|url=https://spectrum.ieee.org/three-chips-in-one-the-history-of-the-bcd-integrated-circuit|title=Three Chips in One: The History of the BCD Integrated Circuit - IEEE Spectrum|website=[[IEEE]]}}</ref> [[Applied Materials]] developed the first practical multi chamber, or cluster wafer processing tool, the Precision 5000.<ref>{{cite web | url=https://www.chiphistory.org/141-applied-materials-precision-5000-cvd | title=Applied Materials Precision 5000 CVD System }}</ref>

Until the 1980s, physical vapor deposition was the primary technique used for depositing materials onto wafers, until the advent of chemical vapor deposition.<ref>{{cite web | url=https://www.chiphistory.org/110-mrc-series-900-in-line-sputtering-system | title=Series 900 In-Line Sputtering System by MRC }}</ref> Equipment with diffusion pumps was replaced with those using turbomolecular pumps as the latter do not use oil which often contaminated wafers during processing in vacuum.<ref>{{cite book | url=https://books.google.com/books?id=i_brZUv8JEYC&dq=turbomolecular+pump+replaced+diffusion+pump&pg=PA72 | isbn=978-1-4377-7868-7 | title=Vacuum Deposition onto Webs, Films and Foils | date=21 June 2011 | publisher=William Andrew }}</ref>

200&nbsp;mm diameter wafers were first used in 1990 and became the standard until the introduction of 300&nbsp;mm diameter wafers in 2000.<ref>{{Cite conference|url=https://ieeexplore.ieee.org/document/993612|title=The world's first 300 mm fab at Infineon - challenges and success |book-title=Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) |doi=10.1109/ISSM.2000.993612 |s2cid=109383925 }}</ref><ref>{{cite web | url=https://www.edn.com/the-300mm-era-begins/ | title=The 300mm Era Begins | date=10 July 2000 }}</ref> Bridge tools were used in the transition from 150&nbsp;mm wafers to 200&nbsp;mm wafers<ref name="auto12">{{cite web | url=https://www.chiphistory.org/711-applied-materials-introduces-producer-wafer-fab-system | title=Applied Materials Producer }}</ref> and in the transition from 200&nbsp;mm to 300&nbsp;mm wafers.<ref>{{Cite web|url=http://www.chiphistory.org/878-300mm-semiconductor-wafers-get-a-reprieve|title=300mm Semiconductor Wafers get a reprieve|website=Chip History}}</ref><ref>{{cite web | url=https://www.eetimes.com/novellus-offers-300-mm-cvd-tool-thats-smaller-than-200-mm-lower-costs/ | title=Novellus offers 300-mm CVD tool that's smaller than 200-mm, lower costs | date=10 July 2000 }}</ref> The semiconductor industry has adopted larger wafers to cope with the increased demand for chips as larger wafers provide more surface area per wafer.<ref>{{cite conference|url=https://pubs.aip.org/aip/acp/article/449/1/97/975569/Model-based-silicon-wafer-criteria-for-optimal|title=Model-based silicon wafer criteria for optimal integrated circuit performance|first1=Howard R. |last1=Huff |first2=Randal K. |last2=Goodall |first3=W. Murray |last3=Bullis |first4=James A. |last4=Moreland |first5=Fritz G. |last5=Kirscht |first6=Syd R. |last6=Wilson |author7=The NTRS Starting Materials Team |book-title=AIP Conference Proceedings |volume=449 |issue=1 |pages=97–112 |date=24 November 1998 |doi=10.1063/1.56795}}</ref> Over time, the industry shifted to 300&nbsp;mm wafers which brought along the adoption of FOUPs,<ref name="auto11">{{cite book | url=https://books.google.com/books?id=3S-GDwAAQBAJ&dq=before+smif+wafers&pg=PT40 | title=Wafer Fabrication: Automatic Material Handling System | isbn=978-3-11-048723-7 | last1=Zhang | first1=Jie | date=24 September 2018 | publisher=Walter de Gruyter GmbH & Co KG }}</ref> but many products that are not advanced are still produced in 200&nbsp;mm wafers such as analog ICs, RF chips, power ICs, BCDMOS and [[MEMS]] devices.<ref>{{Cite web|url=https://semiengineering.com/200mm-fab-crunch/|title=200mm Fab Crunch|first=Mark|last=LaPedus|date=May 21, 2018|website=Semiconductor Engineering}}</ref> 

Some processes such as cleaning,<ref>{{cite web |url=https://www.eetimes.com/the-future-of-batch-and-single-wafer-processing-in-wafer-cleaning/ |title=The future of batch and single-wafer processing in wafer cleaning |first=Scott |last=Becker |date=24 March 2003 |website=[[EE Times]]}}</ref> ion implantation,<ref>{{cite conference | url=https://ieeexplore.ieee.org/document/586424 | title=Manufacturing advantages of single wafer high current ion implantation |book-title=Proceedings of 11th International Conference on Ion Implantation Technology | doi=10.1109/IIT.1996.586424 | s2cid=70599233 }}</ref><ref>{{cite journal | url=https://doi.org/10.1016/j.nimb.2005.05.016 | doi=10.1016/j.nimb.2005.05.016 | title=Approaches to single wafer high current ion implantation | date=2005 | last1=Renau | first1=A. | journal=Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms | volume=237 | issue=1–2 | pages=284–289 | bibcode=2005NIMPB.237..284R }}</ref> etching,<ref>{{cite book | url=https://books.google.com/books?id=xQ3yBwAAQBAJ&dq=batch+plasma+etching&pg=PA199 | isbn=978-1-4899-2566-4 | title=Dry Etching for VLSI | date=29 June 2013 | publisher=Springer }}</ref> annealing<ref>{{cite journal | url=https://link.springer.com/article/10.1557/PROC-470-201 | doi=10.1557/PROC-470-201 | title=Understanding the Impact of Batch vs. Single Wafer in Thermal Processing Using Cost of Ownership Analysis | date=1997 | last1=Hossain-Pas | first1=S. | last2=Pas | first2=M. F. | journal=MRS Proceedings | volume=470 }}</ref> and oxidation<ref>{{cite journal | url=https://ieeexplore.ieee.org/document/1198020 | title=Contrasting single-wafer and batch processing for memory devices |journal=IEEE Transactions on Semiconductor Manufacturing | date=2003 |volume=16 |issue=2 | doi=10.1109/TSM.2003.810939 | last1=Weimer | first1=R.A. | last2=Eppich | first2=D.M. | last3=Beaman | first3=K.L. | last4=Powell | first4=D.C. | last5=Gonzalez | first5=F. | pages=138–146 }}</ref> started to adopt single wafer processing instead of batch wafer processing in order to improve the reproducibility of results.<ref>{{cite book | url=https://books.google.com/books?id=TzL5aUslKDUC&dq=batch+single+wafer+etching&pg=PA309 | isbn=978-0-470-02056-2 | title=Introduction to Microfabrication | date=28 January 2005 | publisher=John Wiley & Sons }}</ref><ref>{{cite conference | url=https://ieeexplore.ieee.org/document/200629 | title=Trends in single-wafer processing |book-title=1992 Symposium on VLSI Technology Digest of Technical Papers | doi=10.1109/VLSIT.1992.200629 | s2cid=110840307 }}</ref> A similar trend existed in MEMS manufacturing.<ref>{{cite web | url=https://www.cmmmagazine.com/mems/single-wafer-vs-batch-wafer-processing-in-mems-manufacturing/ | title=Single Wafer vs Batch Wafer Processing in MEMS Manufacturing | date=2 August 2016 | access-date=18 February 2024 | archive-date=18 February 2024 | archive-url=https://web.archive.org/web/20240218221103/https://www.cmmmagazine.com/mems/single-wafer-vs-batch-wafer-processing-in-mems-manufacturing/ | url-status=dead }}</ref> In 1998, Applied Materials introduced the Producer, a cluster tool that had chambers grouped in pairs for processing wafers, which shared common vacuum and supply lines but were otherwise isolated, which was revolutionary at the time as it offered higher productivity than other cluster tools without sacrificing quality, due to the isolated chamber design.<ref>{{Cite web|url=http://www.chiphistory.org/712-applied-materials-producer-a-new-revolution-is-upon-us|title=Applied Materials Producer - a new revolution is upon us|website=Chip History}}</ref><ref name="auto12"/>

===21st century===
[[File:Intel Fab 12, Fab 22, Fab 32.jpg|thumb|Intel facilities in Chandler Arizona]]
The [[semiconductor industry]] is a global business today. The leading semiconductor manufacturers typically have facilities all over the world. [[Samsung Electronics]], the world's largest manufacturer of semiconductors, has facilities in South Korea and the US. [[Intel]], the second-largest manufacturer, has facilities in Europe and Asia as well as the US. [[TSMC]], the world's largest [[Foundry model|pure play foundry]], has facilities in Taiwan, China, Singapore, and the US. [[Qualcomm]] and [[Broadcom]] are among the biggest [[fabless]] semiconductor companies, outsourcing their production to companies like TSMC.<ref>{{Cite news|url=http://anysilicon.com/top-10-worldwide-semiconductor-sales-leaders-q1-2017/|title=Top 10 Worldwide Semiconductor Sales Leaders - Q1 2017 - AnySilicon|date=2017-05-09|work=AnySilicon|access-date=2017-11-19|language=en-US|archive-date=2017-11-06|archive-url=https://web.archive.org/web/20171106231204/http://anysilicon.com/top-10-worldwide-semiconductor-sales-leaders-q1-2017/|url-status=live}}</ref> They also have facilities spread in different countries. As the average utilization of semiconductor devices increased, durability became an issue and manufacturers started to design their devices to ensure they last for enough time, and this depends on the market the device is designed for. This especially became a problem at the 10&nbsp;nm node.<ref>{{Cite web|url=https://semiengineering.com/transistor-aging-intensifies-10nm/|title=Transistor Aging Intensifies At 10/7nm And Below|first=Ann|last=Mutschler|date=July 13, 2017|website=Semiconductor Engineering}}</ref><ref>{{Cite web|url=https://semiengineering.com/chip-aging-accelerates/|title=Chip Aging Accelerates|first=Ed|last=Sperling|date=February 14, 2018|website=Semiconductor Engineering}}</ref>

[[Silicon on insulator]] (SOI) technology has been used in [[AMD]]'s 130&nbsp;nm, 90&nbsp;nm, 65&nbsp;nm, 45&nbsp;nm and 32&nbsp;nm single, dual, quad, six and eight core processors made since 2001.<ref>{{cite web |last=de Vries |first=Hans |date= |title=Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed. |url=http://chip-architect.com/news/2000_11_07_process_130_nm.html |access-date=22 April 2018 |website=chip-architect.com}}</ref> During the transition from 200&nbsp;mm to 300&nbsp;mm wafers in 2001, many bridge tools were used which could process both 200&nbsp;mm and 300&nbsp;mm wafers.<ref>{{cite web | url=https://www.edn.com/bridge-tools-appear-to-be-taking-over-300-mm-movement/ | title='Bridge tools' appear to be taking over 300-mm movement | date=26 April 2001 }}</ref> At the time, 18 companies could manufacture chips in the leading edge 130nm process.<ref>{{cite web | url=https://semiengineering.com/foundry-wars-begin/ | title=Foundry Wars Begin | date=19 April 2021 }}</ref>

In 2006, 450&nbsp;mm wafers were expected to be adopted in 2012, and 675&nbsp;mm wafers were expected to be used by 2021.<ref>{{cite web | url=https://www.eetimes.com/get-ready-for-675-mm-fabs-in-2021/ | title=Get ready for 675-mm fabs in 2021 | date=14 November 2006 }}</ref>

[[File:Semiconductor photomask.jpg|thumb|Semiconductor photomask or reticle]]
Since 2009, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch.<ref>{{cite web|url=https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html|title=A Brief History of Process Node Evolution|last=Shukla|first=Priyank|website=design-reuse.com|access-date=2019-07-09|archive-date=2019-07-09|archive-url=https://web.archive.org/web/20190709064439/https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html|url-status=live}}</ref><ref>{{cite news|url=https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists|title=14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists…|last=Hruska|first=Joel|website=[[ExtremeTech]]|date=23 June 2014 |access-date=2019-07-09|archive-date=2019-07-09|archive-url=https://web.archive.org/web/20190709064438/https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists|url-status=live}}</ref><ref>{{cite web|url=https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/|title=Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022|website=wccftech.com|date=2016-09-10|access-date=2019-07-09|archive-date=2019-07-09|archive-url=https://web.archive.org/web/20190709064438/https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/|url-status=live}}</ref> For example, [[GlobalFoundries]]' [[7&nbsp;nm]] process was similar to Intel's [[10 nm process]], thus the conventional notion of a process node has become blurred.<ref>{{cite web|url=https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/|title=Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms|website=eejournal.com|date=2018-03-12|access-date=2019-07-09|archive-date=2019-07-09|archive-url=https://web.archive.org/web/20190709064439/https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/|url-status=live}}</ref> Additionally, TSMC and Samsung's 10&nbsp;nm processes are only slightly denser than Intel's 14&nbsp;nm in transistor density. They are actually much closer to Intel's 14&nbsp;nm process than they are to Intel's 10&nbsp;nm process (e.g. Samsung's 10&nbsp;nm processes' fin pitch is the exact same as that of Intel's 14&nbsp;nm process: 42&nbsp;nm).<ref>{{Cite web|url=https://en.wikichip.org/wiki/10_nm_lithography_process#Industry|title=10 nm lithography process - WikiChip|website=en.wikichip.org|access-date=2019-08-17|archive-date=2019-07-01|archive-url=https://web.archive.org/web/20190701083338/https://en.wikichip.org/wiki/10_nm_lithography_process#Industry|url-status=live}}</ref><ref>{{Cite web|url=https://en.wikichip.org/wiki/14_nm_lithography_process#Industry|title=14 nm lithography process - WikiChip|website=en.wikichip.org|access-date=2019-08-17|archive-date=2019-07-01|archive-url=https://web.archive.org/web/20190701083339/https://en.wikichip.org/wiki/14_nm_lithography_process#Industry|url-status=live}}</ref> Intel has changed the name of its 10&nbsp;nm process to position it as a 7&nbsp;nm process.<ref>{{cite web | url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros | title=Intel's Process Roadmap to 2025: With 4nm, 3nm, 20A and 18A?! | last=Cutress | first=Ian | website=[[AnandTech]]}}</ref> As transistors become smaller, new effects start to influence design decisions such as self-heating of the transistors, and other effects such as electromigration have become more evident since the 16nm node.<ref>{{Cite web|url=https://semiengineering.com/chip-aging-becomes-design-problem/|title=Chip Aging Becomes Design Problem|first=Brian|last=Bailey|date=August 9, 2018|website=Semiconductor Engineering}}</ref><ref>{{Cite web|url=https://semiengineering.com/will-self-heating-stop-finfets/|title=Will Self-Heating Stop FinFETs|first=Katherine|last=Derbyshire|date=April 20, 2017|website=Semiconductor Engineering}}</ref>

In 2011, [[Intel]] demonstrated [[Fin field-effect transistor]]s (FinFETs), where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors at the 22nm node, because planar transistors which only have one surface acting as a channel, started to suffer from short channel effects.<ref>{{cite web | url=https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/finfet-3/ | title=FinFET }}</ref><ref>{{cite web | url=https://spectrum.ieee.org/foundries-rush-3d-transistors | title=Foundries Rush 3-D Transistors - IEEE Spectrum }}</ref><ref>{{Cite web|url=http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf|title=Intel's Revolutionary 22 nm Transistor Technology|last1=Bohr|first1=Mark|last2=Mistry|first2=Kaizad|date=May 2011|website=intel.com|access-date=April 18, 2018}}</ref><ref>{{Cite news|url=https://www.techradar.com/news/computing-components/processors/intel-s-tri-gate-transistors-everything-you-need-to-know-952572|title=Intel's Tri-Gate transistors: everything you need to know|last=Grabham|first=Dan|date=May 6, 2011|work=TechRadar|access-date=April 19, 2018}}</ref><ref>
{{cite journal |doi=10.1109/MM.2017.4241347|title=CMOS Scaling Trends and Beyond|journal=IEEE Micro|volume=37|issue=6|pages=20–29|year=2017|last1=Bohr|first1=Mark T.|last2=Young|first2=Ian A.
|s2cid=6700881|quote=The next major transistor innovation was the introduction of FinFET (tri-gate) transistors on Intel's 22-nm technology in 2011.}}
</ref> A startup called SuVolta created a technology called Deeply Depleted Channel (DDC) to compete with FinFET transistors, which uses planar transistors at the 65&nbsp;nm node which are very lightly doped.<ref>{{cite web | url=https://spectrum.ieee.org/startup-seeks-new-life-for-planar-transistors | title=Start-up Seeks New Life for Planar Transistors - IEEE Spectrum }}</ref>

By 2018, a number of transistor architectures had been proposed for the eventual replacement of [[FinFET]], most of which were based on the concept of [[GAAFET]]:<ref>{{cite web | url=https://semiengineering.com/the-increasingly-uneven-race-to-3nm-2nm/ | title=The Increasingly Uneven Race to 3nm/2nm | date=24 May 2021 }}</ref> horizontal and vertical nanowires, horizontal nanosheet transistors<ref>{{cite web | url=https://semiengineering.com/whats-different-about-next-gen-transistors/ | title=What's Different About Next-Gen Transistors | date=20 October 2022 }}</ref><ref>{{cite web | url=https://spectrum.ieee.org/amp/intels-stacked-nanosheet-transistors-could-be-the-next-step-in-moores-law-2652903505 | title=Intel's Stacked Nanosheet Transistors Could be the Next Step in Moore's Law }}</ref> (Samsung MBCFET, Intel Nanoribbon), vertical FET (VFET) and other vertical transistors,<ref>{{cite web | url=https://spectrum.ieee.org/amp/nanowire-transistors-could-keep-moores-law-alive-2650269271 | title=Nanowire Transistors Could Keep Moore's Law Alive }}</ref><ref>{{cite web | url=https://physicsworld.com/a/nanowires-give-vertical-transistors-a-boost/ | title=Nanowires give vertical transistors a boost | date=2 August 2012 }}</ref> complementary FET (CFET), stacked FET, vertical TFETs, FinFETs with III-V semiconductor materials (III-V FinFET),<ref>{{cite web | url=https://arstechnica.com/gadgets/2016/07/itrs-roadmap-2021-moores-law/?amp=1 | title=Transistors will stop shrinking in 2021, but Moore's law will live on | date=25 July 2016 }}</ref><ref>{{Cite web|url=https://www.extremetech.com/science/162376-7nm-5nm-3nm-the-new-materials-and-transistors-that-will-take-us-to-the-limits-of-moores-law|title=7nm, 5nm, 3nm: The new materials and transistors that will take us to the limits of Moore's law &#124; Extremetech|date=26 July 2013 }}</ref> several kinds of horizontal gate-all-around transistors such as nano-ring, hexagonal wire, square wire, and round wire gate-all-around transistors<ref>{{cite web | url=https://semiengineering.com/whats-after-finfets/ | title=What's After FinFETs? | date=24 July 2017 }}</ref> and negative-capacitance FET (NC-FET) which uses drastically different materials.<ref>{{cite web | url=https://semiengineering.com/transistor-options-beyond-3nm/ | title=Transistor Options Beyond 3nm | date=15 February 2018 }}</ref> FD-SOI was seen as a potential low cost alternative to FinFETs.<ref>{{cite web | url=https://www.eetimes.com/samsung-gf-ramp-fd-soi/ | title=Samsung, GF Ramp FD-SOI | date=27 April 2018 }}</ref>

As of 2019, [[14 nanometer]] and [[10 nanometer]] chips are in mass production by Intel, [[United Microelectronics Corporation|UMC]], TSMC, Samsung, [[Micron Technology|Micron]], [[SK Hynix]], [[Toshiba Memory]] and GlobalFoundries, with [[7 nanometer]] process chips in mass production by TSMC and Samsung, although their 7 nanometer node definition is similar to Intel's 10 nanometer process. The [[5 nanometer]] process began being produced by Samsung in 2018.<ref>{{Cite web|url=https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology|title=Samsung Completes Development of 5nm EUV Process Technology|last=Shilov|first=Anton|website=[[AnandTech]]|access-date=2019-05-31|archive-date=2019-04-20|archive-url=https://web.archive.org/web/20190420144452/https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology|url-status=live}}</ref> As of 2019, the node with the highest [[transistor density]] is TSMC's 5{{nbsp}}nanometer N5 node,<ref>{{cite web |last1=Cheng |first1=Godfrey |title=Moore's Law is not Dead |url=https://www.tsmc.com/english/news-events/blog-article-20190814 |website=TSMC Blog |publisher=[[TSMC]] |date=14 August 2019 |access-date=25 September 2023}}</ref> with a density of 171.3{{nbsp}}million transistors per square millimeter.<ref>{{Cite web|url=https://fuse.wikichip.org/news/2207/tsmc-starts-5-nanometer-risk-production/|title=TSMC Starts 5-Nanometer Risk Production|last=Schor|first=David|date=2019-04-06|website=WikiChip Fuse|language=en-US|access-date=2019-04-07|archive-date=2020-05-05|archive-url=https://web.archive.org/web/20200505020415/https://fuse.wikichip.org/news/2207/tsmc-starts-5-nanometer-risk-production/|url-status=live}}</ref> In 2019, Samsung and TSMC announced plans to produce [[3 nanometer]] nodes. GlobalFoundries has decided to stop the development of new nodes beyond 12 nanometers in order to save resources, as it has determined that setting up a new fab to handle sub-12&nbsp;nm orders would be beyond the company's financial abilities.<ref>{{Cite web|url=https://www.anandtech.com/show/13277/globalfoundries-stops-all-7nm-development|title=GlobalFoundries Stops All 7nm Development: Opts To Focus on Specialized Processes|first1=Anton|last1=Shilov|first2=Ian|last2=Cutress|website=[[AnandTech]]|access-date=2019-10-12|archive-date=2019-10-12|archive-url=https://web.archive.org/web/20191012175428/https://www.anandtech.com/show/13277/globalfoundries-stops-all-7nm-development|url-status=live}}</ref>

From 2020 to 2022, there was a [[Global chip shortage (2020–2023)|global chip shortage]]. During this shortage caused by the COVID-19 pandemic, many semiconductor manufacturers banned employees from leaving company grounds.<ref>{{cite news | url=https://www.telegraph.co.uk/world-news/2021/06/25/taiwan-chipmakers-keep-workers-imprisoned-factories-keep-global/ | title=Taiwan chipmakers keep workers 'imprisoned' in factories to keep up with global pandemic demand | newspaper=The Telegraph | date=July 2021 | last1=Smith | first1=Nicola | last2=Liu | first2=John }}</ref> Many countries granted subsidies to semiconductor companies for building new fabrication plants or fabs. Many companies were affected by counterfeit chips.<ref>{{cite web | url=https://arstechnica.com/gadgets/2021/06/chip-shortages-lead-to-more-counterfeit-chips-and-devices/?amp=1 | title=Chip shortages lead to more counterfeit chips and devices | date=14 June 2021 }}</ref> Semiconductors have become vital to the world economy and the national security of some countries.<ref>{{cite interview|url=https://www.weforum.org/podcasts/radio-davos/episodes/silicon-chips-semiconductors-chris-miller/|title=What are semiconductors, and why are they vital to the global economy?|first=Chris|last=Miller|website=[[World Economic Forum]]}}</ref><ref>{{cite news|url=https://www.washingtonpost.com/technology/2021/06/14/global-subsidies-semiconductors-shortage/|title=Countries lavish subsidies and perks on semiconductor manufacturers as a global chip war heats up|first=Jeanne|last=Whalen|date=June 14, 2021|newspaper=[[The Washington Post]]}}</ref><ref>{{cite news|url=https://www.reuters.com/technology/us-launching-semiconductor-supply-chain-review-boost-national-security-2023-12-21/|title=China import concerns spur US to launch semiconductor supply chain review|first=David|last=Shepardson|date=December 21, 2023|website=Reuters}}</ref> The US has asked TSMC to not produce semiconductors for Huawei, a Chinese company.<ref>{{cite news | url=https://www.ft.com/content/6ab43e94-fca8-11e9-a354-36acbbb0d9b6 | title=US urges Taiwan to curb chip exports to China | newspaper=Financial Times | date=3 November 2019 | last1=Hille | first1=Kathrin }}</ref> CFET transistors were explored, which stacks NMOS and PMOS transistors on top of each other. Two approaches were evaluated for constructing these transistors: a monolithic approach which built both types of transistors in one process, and a sequential approach which built the two types of transistors separately and then stacked them.<ref name="auto10">{{cite web | url=https://semiwiki.com/events/300552-vlsi-technology-forum-short-course-logic-devices/ | title=VLSI Symposium - TSMC and Imec on Advanced Process and Devices Technology Toward 2nm | date=25 February 2024 }}</ref>