Editing SPARC (section)

==History==
There have been three major revisions of the architecture. The first published version was the 32-bit ''SPARC version 7'' (V7) in 1986. ''SPARC version 8'' (V8), an enhanced SPARC architecture definition, was released in 1990.  The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended-precision" floating-point arithmetic to 128-bit "[[quadruple-precision floating-point format|quad-precision]]" arithmetic.  SPARC V8 served as the basis for IEEE Standard 1754-1994, an [[IEEE]] standard for a 32-bit microprocessor architecture.

''SPARC version 9'', the 64-bit SPARC architecture, was released by SPARC International in 1993.  It was developed by the SPARC Architecture Committee consisting of [[Amdahl Corporation]], [[Fujitsu]], [[International Computers Limited|ICL]], [[LSI Logic]], [[Panasonic|Matsushita]], [[Philips]], [[Ross Technology]], [[Sun Microsystems]], and [[Texas Instruments]]. Newer specifications always remain compliant with the full SPARC V9 Level 1 specification.

In 2002, the SPARC ''Joint Programming Specification 1'' (JPS1) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements".

At the end of 2003, JPS2 was released to support multicore CPUs. The first CPUs conforming to JPS2 were the UltraSPARC IV by Sun and the SPARC64 VI by Fujitsu.

In early 2006, Sun released an extended architecture specification, ''UltraSPARC Architecture 2005''. This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions developed through the processor generations of UltraSPARC III, IV, and IV+, as well as CMT extensions starting with the [[UltraSPARC T1]] implementation:

* the [[Visual Instruction Set|VIS]] 1 and VIS 2 instruction set extensions and the associated GSR register
* multiple levels of global registers, controlled by the GL register
* Sun's 64-bit MMU architecture
* privileged instructions ALLCLEAN, OTHERW, NORMALW, and INVALW
* access to the VER register is now hyperprivileged
* the SIR instruction is now hyperprivileged

In 2007, Sun released an updated specification, ''UltraSPARC Architecture 2007'', to which the [[UltraSPARC T2]] implementation complied.

In December 2007, Sun also made the [[UltraSPARC T2]] processor's RTL available via the [[OpenSPARC]] project.<ref>{{cite web |title=Sun Accelerates Growth of UltraSPARC CMT Eco System |url=http://www.sun.com/pr/2007-12/sunflash.20071211.1.xml |publisher=Sun Microsystems |archive-url=https://web.archive.org/web/20080126174236/http://www.sun.com/aboutsun/pr/2007-12/sunflash.20071211.1.xml |archive-date=January 26, 2008 |url-status=dead}}</ref> It was also released under the GNU General public license v2.<ref>{{cite web|archiveurl=https://web.archive.org/web/20121017041211/http://www.oracle.com/technetwork/systems/opensparc/opensparc-faq-1444660.html|url=http://www.oracle.com/technetwork/systems/opensparc/opensparc-faq-1444660.html|title=OpenSPARC Frequently Asked Questions|publisher=Oracle|archivedate=2012-10-17|access-date=2021-03-20}}</ref> OpenSPARC T2 is 8 cores, 16 pipelines with 64 threads.

In August 2012, Oracle Corporation made available a new specification, ''Oracle SPARC Architecture 2011'', which besides the overall update of the reference, adds the VIS 3 instruction set extensions and [[Logical Domains|hyperprivileged mode]] to the 2007 specification.<ref name="sparc-arch-2011" />

In October 2015, Oracle released SPARC M7, the first processor based on the new ''Oracle SPARC Architecture 2015'' specification.<ref name="SPARC 2015" /><ref>{{cite web
| url = https://www.oracle.com/us/corporate/features/sparc-m7/
| title = SPARC M7 Innovation
| access-date = October 13, 2015
| last=Soat |first=John
| work = Oracle web site
| publisher = [[Oracle Corporation]]
| archive-date = September 5, 2015
| archive-url = https://web.archive.org/web/20150905065312/http://www.oracle.com/us/corporate/features/sparc-m7/
| url-status = live
}}</ref>  This revision includes VIS 4 instruction set extensions and hardware-assisted encryption and silicon secured memory (SSM).<ref>{{cite web|url=https://www.oracle.com/servers/sparc/software-in-silicon.html|title=Software in Silicon Cloud - Oracle|website=www.oracle.com|access-date=January 21, 2019|archive-date=January 21, 2019|archive-url=https://web.archive.org/web/20190121185630/https://www.oracle.com/servers/sparc/software-in-silicon.html|url-status=live}}</ref>

SPARC architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 through the Sun UltraSPARC Architecture implementations.

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for [[Standard Performance Evaluation Corporation|SPEC]] CPU95 and CPU2000 benchmarks. The 296&nbsp;MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.