Editing Phase-locked loop (section)

=== Clock analogy ===
Phase can be proportional to [[time]],{{Efn|If the frequency is constant and the initial phase is zero, then the phase of a sinusoid is proportional to time.}} so a phase difference can correspond to a time difference.

Left alone, different clocks will mark time at slightly different rates. A [[mechanical clock]], for example, might be fast or slow by a few seconds per hour compared to a reference [[atomic clock]] (such as the [[NIST-F2]]). That time difference becomes substantial over time. Instead, the owner can synchronize their mechanical clock (with varying degrees of accuracy) by phase-locking it to a reference clock.

An inefficient synchronization method involves the owner resetting their clock to that more accurate clock's time every week. But, left alone, their clock will still continue to diverge from the reference clock at the same few seconds per hour rate.

A more efficient synchronization method (analogous to the simple PLL in Figure 1) utilizes the fast-slow timing adjust control (analogous to how the VCO's frequency can be adjusted) available on some clocks. Analogously to the phase comparator, the owner could notice their clock's misalignment and turn its timing adjust a small proportional amount to make their clock's frequency a little slower (if their clock was fast) or faster (if their clock was slow). If they don't overcompensate, then their clock will be more accurate than before. Over a series of such weekly adjustments, their clock's notion of a second would agree close enough with the reference clock, so they could be said to be locked both in frequency and phase.

An early [[electromechanical]] version of a phase-locked loop was used in 1921 in the [[Shortt-Synchronome clock]].