Editing Peripheral Component Interconnect (section)

==Auto configuration==
PCI provides separate memory and [[memory-mapped I/O]] port address spaces for the [[x86]] processor family, [[64-bit computing|64]] and [[32-bit computing|32 bits]], respectively.  Addresses in these [[address space]]s are assigned by software.  A third address space, called the [[PCI Configuration Space]], which uses a fixed addressing scheme, allows software to determine the amount of memory and I/O address space needed by each device. Each device can request up to six areas of memory space or [[input/output]] (I/O) port space via its configuration space registers.

In a typical system, the [[firmware]] (or [[operating system]]) queries all PCI buses at startup time (via [[PCI Configuration Space]]) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs. It then allocates the resources and tells each device what its allocation is.

The PCI configuration space also contains a small amount of device type information, which helps an operating system choose device drivers for it, or at least to have a dialogue with a user about the system configuration.

Devices may have an on-board [[read-only memory]] (ROM) containing executable code for x86 or [[PA-RISC]] processors, an [[Open Firmware]] driver, or an [[Option ROM]]. These are typically needed for devices used during system startup, before device drivers are loaded by the operating system.

In addition, there are ''PCI Latency Timers'' that are a mechanism for ''PCI Bus-Mastering'' devices to share the PCI bus fairly. "Fair" in this case means that devices will not use such a large portion of the available PCI bus bandwidth that other devices are not able to get needed work done. Note, this does not apply to PCI Express.

{{Blockquote|How this works is that each PCI device that can operate in bus-master mode is required to implement a timer, called the Latency Timer, that limits the time that device can hold the PCI bus. The timer starts when the device gains bus ownership, and counts down at the rate of the PCI clock. When the counter reaches zero, the device is required to release the bus. If no other devices are waiting for bus ownership, it may simply grab the bus again and transfer more data.<ref>{{Cite web
| title = PCI Latency Timer Howto
| publisher = Reric.NET by Eric Seppanen
| date = 2004-11-14
|url=http://www.reric.net/linux/pci_latency.html
| access-date = 2008-07-17
}}
</ref>}}