Editing Multiplexer (section)

==Digital multiplexers==
In [[digital circuit]] design, the selector wires are of digital value. In the case of a 2-to-1 multiplexer, a logic value of 0 would connect <math> I_0</math> to the output, while a logic value of 1 would connect <math> I_1</math> to the output.
In larger multiplexers, the number of selector pins is equal to <math> \left \lceil \log_2(n) \right \rceil</math> where <math> n</math> is the number of inputs.

For example, 9 to 16 inputs would require no fewer than 4 selector pins and 17 to 32 inputs would require no fewer than 5 selector pins. The binary value expressed on these selector pins determines the selected input pin.

A 2-to-1 multiplexer has a [[Boolean equation]] where <math> A</math> and <math> B</math> are the two inputs, <math> S_0</math> is the selector input, and <math> Z</math> is the output:
: <math>Z = ( A \wedge \neg S_0) \vee (B \wedge S_0)</math>  or
: <math>Z = ( A \cdot \overline{S_0}) + (B \cdot S_0)</math>

[[File:Multiplexer 2-to-1.svg|thumb|175px|A 2-to-1 mux]]
Which can be expressed as a [[truth table]]:

{| class="wikitable"
|-
! <math> S_0</math> !! <math> A</math> !! <math> B</math> !! <math> Z</math>
|-
| 0 || 0 || 0 || 0
|-
| 0 || 0 || 1 || 0
|-
| 0 || 1 || 0 || 1
|-
| 0 || 1 || 1 || 1
|-
| 1 || 0 || 0 || 0
|-
| 1 || 0 || 1 || 1
|-
| 1 || 1 || 0 || 0
|-
| 1 || 1 || 1 || 1
|}

Or, in simpler notation:

{| class="wikitable"
|-
! <math> S_0 </math> !! <math> Z </math>
|-
| 0 || A
|-
| 1 || B
|}


These tables show that when <math> S_0 = 0</math> then <math> Z = A</math> but when <math> S_0 = 1</math> then <math> Z = B</math>. A straightforward realization of this 2-to-1 multiplexer would need 2 AND gates, an OR gate, and a NOT gate. While this is mathematically correct, a direct physical implementation would be prone to [[race condition]]s that require additional gates to suppress.<ref>{{cite book |last1=Crowe |first1=John |first2=Barrie |last2=Hayes-Gill |chapter=The multiplexer hazard |chapter-url=https://books.google.com/books?id=97w8luwEIAsC&pg=PA111 |title=Introduction to Digital Electronics |publisher=Elsevier |date=1998 |isbn=9780080534992 |pages=111–3 }}</ref>

Larger multiplexers are also common and, as stated above, require <math> \left \lceil \log_2(n) \right \rceil</math> selector pins for <math>n</math> inputs. Other common sizes are 4-to-1, 8-to-1, and 16-to-1. Since digital logic uses binary values, powers of 2 are used (4, 8, 16) to maximally control a number of inputs for the given number of selector inputs.

<gallery>
File:Multiplexer 4-to-1.svg|4-to-1 mux
File:Multiplexer 8-to-1.svg|8-to-1 mux
File:Multiplexer 16-to-1.svg|16-to-1 mux
</gallery>

The Boolean equation for a 4-to-1 multiplexer is:
:<math>Z = (A \wedge \neg {S_1} \wedge \neg S_0) \vee (B  \wedge \neg S_1 \wedge S_0) \vee (C \wedge S_1 \wedge \neg S_0) \vee (D \wedge S_1 \wedge S_0)</math>  or
:<math>Z = (A \cdot \overline{S_1} \cdot \overline{S_0}) + (B \cdot \overline{S_1}. S_0) + (C \cdot S_1 \cdot \overline{S_0}) + (D \cdot S_1 \cdot S_0)</math>

Which can be expressed as a [[truth table]]:

{| class="wikitable"
|-
! <math> S_1</math> !! <math> S_0</math> !! <math> Z</math>
|-
| 0 || 0 || A
|-
| 0 || 1 || B
|-
| 1 || 0 || C
|-
| 1 || 1 || D
|}

The following 4-to-1 multiplexer is constructed from [[3-state buffers]] and AND gates (the AND gates are acting as the decoder):
[[File:4to1 MUX using basic gates.jpg|alt= 4:1 MUX circuit using 3 input AND and other gates|thumb|396x396px|A  4:1 MUX circuit using 3 input AND and other gates]]
[[File:Mux from 3 state buffers.png|200px]]

The subscripts on the <math> I_n</math> inputs indicate the decimal value of the binary control inputs at which that input is let through.

===Chaining multiplexers and mux trees===
Larger Multiplexers can be constructed by using smaller multiplexers by chaining them together in what are called "mux trees". For example, an 8:1 multiplexer can be made with two 4:1 multiplexers and one 2:1 multiplexer. The two 4:1 multiplexer outputs are fed into the 2:1 with the selector pins on the 4:1's put in parallel giving a total number of selector inputs to 3, which is equivalent to an 8:1.

===List of ICs which provide multiplexing===
[[File:54S157 Signetics 8014 package top.jpg|thumb|[[Signetics]] S54S157 quad 2:1 mux]]
For [[7400 series]] part numbers in the following table, "x" is the logic family.
{| class="wikitable"
|-
!  IC No. !! Function !! Output State
|-
| 74x157
| Quad 2:1 mux.
| Output same as input given
|-
| 74x158
| Quad 2:1 mux.
| Output is inverted input
|-
| 74x153
| Dual 4:1 mux.
| Output same as input
|-
| 74x352
| Dual 4:1 mux.
| Output is inverted input
|-
| 74x151A
| 8:1 mux.
| Both outputs available (i.e., complementary outputs)
|-
| 74x151
| 8:1 mux.
| Output is inverted input
|-
| 74x150
| 16:1 mux.
| Output is inverted input
|}