Editing Motorola 68000 series (section)

==Improvement history==
[[Motorola 68010|68010]]:
* Virtual memory support (restartable instructions)
* 'Loop mode' for faster string and memory library primitives
* Multiply instruction uses 14 fewer clock ticks
* 2&nbsp;[[GiB]] directly accessible memory ([[Motorola 68012|68012]] variant)

[[Motorola 68020|68020]]:
* 32-bit address & [[arithmetic logic unit]] (ALU)
* Three stage [[Pipeline (computing)|pipeline]]
* Instruction [[CPU cache|cache]] of 256 bytes
* Unrestricted word and longword data access (see [[Data structure alignment|alignment]])
* 8× [[multiprocessing]] ability
* Larger multiply (32×32 -> 64 bits) and divide (64÷32 -> 32 bits quotient and 32 bits remainder) instructions, and bit field manipulations
* Addressing modes added [[Addressing mode#Scaled|scaled indexing]] and another level of [[Addressing mode#Memory indirect|indirection]]
* Low cost, EC = 24-bit address

[[Motorola 68030|68030]]:
* Split instruction and data cache of 256&nbsp;[[byte]]s each
* On-chip [[memory management unit]] (MMU) ([[Motorola 68851|68851]])
* Low cost EC = No MMU
* Burst Memory Interface

[[Motorola 68040|68040]]:
* Instruction and data caches of 4&nbsp;[[Kibibyte|KB]] each
* Six stage pipeline
* On-chip [[floating-point unit]] (FPU)
* FPU lacks IEEE [[transcendental function]] ability
* FPU emulation works with 2E71M and later chip revisions
* Low cost LC = No FPU
* Low cost EC = No FPU or MMU

[[Motorola 68060|68060]]:
* Instruction and data caches of 8&nbsp;KB each
* 10 stage pipeline
* Two cycle integer multiplication unit
* [[Branch predictor|Branch prediction]]
* Dual instruction pipeline
* Instructions in the [[address generation unit]] (AGU) and thereby supply the result two cycles before the ALU
* Low cost LC = No FPU
* Low cost EC = No FPU or MMU