Editing Microsequencer (section)

==Complex example==
The [[IBM System/360]] was a series of compatible computers introduced in 1964, many of which were microprogrammed.<ref>{{cite book|url=http://www.bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf|title=IBM System/360 Principles of Operation|id=A22-6821-7|publisher=International Business Machines Corp.|date=September 1968}}</ref> The [[IBM System/360 Model 40|System/360 Model 40]] is a good example of a microprogrammed machine with complex microsequencing.<ref>{{cite book|url=http://www.bitsavers.org/pdf/ibm/360/fe/2040/SY22-2843-1_Model_40_Functional_Units_Mar70.pdf|title=System/360 Model 40 Functional Units|id=SY22-2843-1|publisher=International Business Machines Corp.|date=March 1970}}</ref>

The microstore consists of 4,096 56-bit microinstructions that operate in
a horizontal microprogramming style. The store is addressed by the 12-bit
read-only address register (ROAR). Unlike most registers in the
S/360 architecture, bits in the ROAR are numbered from bit 0 on the right
to bit 11 on the left.
<pre>
  +------------+
  |    ROAR    |
  +------------+
  11          0
</pre>

The model 40 performs no sequential execution of microinstructions and
therefore the microsequencer doesn't really branch in the conventional
sense. Instead, each microinstruction specifies the address of the next one
to be executed. Four fields in the microinstruction contribute to the new
address.

* CA, 4 bits: Part of the next address, depending on the other fields.
* CB, 4 bits: Determines bit 1 of the next address.
* CC, 4 bits: Determines bit 0 of the next address.
* CD, 2 bits: Controls how the next address is assembled (except when the CB field contains 15).

There are essentially three combinations or formats of these fields.

=== Functional branch format ===
When the CB field contains 15, a ''functional branch'' occurs. The bits of
the new microstore address in the ROAR are determined as follows.
* bits 11&ndash;10: CD field
* bits 9&ndash;6: CA field
* bit 5: always 0
* bits 4&ndash;1: high-order 4 bits of the Q register, which is the right input to the 8-bit ALU
* bit 0: result of the test specified by the CC field

The CC field can specify various tests of the state of the machine. It can
also specify a constant 0 or 1 for an unconditional bit. 

This format alters the flow of control to 1 of 16 instruction ''pairs''
within the low 32 words of a 64-word block of microstore (because bit 5 is
always 0).  The CC field then determines which instruction of the pair
receives control.

=== CD = 0, 1, 3 format ===
When the CD field is 0, 1, or 3, flow of control is directed to an
instruction within the current 64-word block. The bits of the new microstore
address are determined as follows.
* bits 11&ndash;6: remain the same
* bits 5&ndash;2: CA field
* bit 1: if CD = 0, result of the test specified by the CB field; otherwise 0
* bit 0: result of the test specified by the CC field

The CA field selects 1 of 16 4-word groups within the current 64-word block.
The CB and CC fields then determine which instruction of the 4 receives
control.

=== CD = 2 format ===
When the CD field is 2, flow of control is directed in a nonobvious manner. The
bits of the new microstore address are determined as follows:
* bits 11&ndash;10: remain the same
* bits 9&ndash;6: CA field
* bits 5&ndash;2: remain the same
* bit 1: result of the test specified by the CB field
* bit 0: result of the test specified by the CC field

The next instruction is in the same 1K-word region as the current
instruction, because bits 11&ndash;10 remain the same. The CA field determines
the 64-word block within the region. The instruction is in the same 4-word
group within the new block as the current instruction is within the current
block, because bits 5&ndash;2 remain the same.
The CB and CC fields then determine which instruction of the 4 receives
control.

=== Simplification ===
This description has been simplified. It ignores the following features.
* The model 40 can run in CPU mode or channel mode. The description addresses only CPU mode.
* If the microinstruction is not in functional branch format and the CD field is 1 or 3, bit 1 of the next address is always 0. In this case, the values of the CD and CB fields determine one of a set of control lines to raise.