Editing Memory management unit (section)

=== Segmented translation ===
In segmented translation, a memory address contains a segment number and an offset within the segment. [[Memory segmentation|Segments]] are variable-length, and may have permissions, such as read, write, and execute, associated with them.<ref name="glaser1965">{{cite conference
|title=System Design of a Computer for Time Sharing Applications
|last1=Glaser
|first1=Edward L.
|first2=John F.
|first3=G. A.
|last2=Couleur
|last3=Oliver
|date=1965
|conference=1965 Fall Joint Computer Conference
|url=https://multicians.org/fjcc2.html}}
</ref> A segment is loaded into a contiguous area of physical memory. Typically, the segment number is used as an index into a ''segment table''; each entry in the segment table holds the address of the area of physical memory, the length of the segment, and other information such as permission flags.

This style has the advantage of simplicity; the memory blocks are continuous and thus only the two values, base and limit, need to be stored for mapping purposes.

The disadvantage of this approach is that it leads to an effect known as ''[[external fragmentation]]''. This occurs when memory allocations are released but are non-contiguous. In this case, enough memory may be available to handle a request, but this is spread out and cannot be allocated to a single segment. On systems where programs start and stop over time, this can eventually lead to memory being highly fragmented and no large blocks remaining; in this case, segments would need to be moved in memory, and their segment table entries modified to reflect the new physical address, to make a contiguous space large enough for a segment available.

Some models of the [[PDP-11]] [[16-bit computing|16-bit]] [[minicomputer]] have a segmented memory management unit with a set of ''page address registers'' (PARs) and ''page description registers'' (PDRs); this maps an 16-bit virtual address to an 18-bit physical address. The [[PDP-11/70]] expands that to produce a 22-bit physical address.<ref>{{cite book |title=PDP-11/70 Processor Handbook |publisher=DEC |date=1977 |url=https://bitsavers.org/pdf/dec/pdp11/1170/PDP-11_70_Handbook_1977-78.pdf |chapter=6}}</ref>

Segmenting was widely used on [[microcomputer]] platforms of the 1980s. Among the MMUs that used this concept were the [[Motorola 68451]]<ref name=Zehr/> and the [[Zilog Z8010]], but many other examples exist.

The [[Intel 8086]], [[Intel 8088]], [[Intel 80186]], and [[Intel 80188]] provide crude memory segmentation and no [[memory protection]]. (Every byte of every segment is always available to any program.) The 16-bit segment registers allow for 65,536 segments; each segment begins at a fixed offset equal to 16 times the segment number; the segment starting address granularity is 16 bytes. Each segment grants read-write access to 64&nbsp;KiB (65,536 bytes) of address space (this limit is set by the 16-bit PC and SP registers; the processor does no bounds checking). Offset+address exceeding 0xFFFFF wraps around to 0x00000. Each 64&nbsp;KiB segment overlaps the next 4,095 segments; each physical address can be denoted by 4,096 segment–offset pairs. This scheme can address only 1&nbsp;MiB (1024&nbsp;KiB) of physical memory (and memory-mapped i/o). (Optional [[expanded memory]] hardware can add bank-switched memory under software control.) Later [[x86]] processors, starting with the [[Intel 80286]], supported real segmented mapping, with a segment table.